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11.发明申请公开(公告)号：US20070210414A1
公开(公告)日：2007-09-13
申请号：US11683053
申请日：2007-03-07
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。
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公开(公告)号：US20130049166A1
公开(公告)日：2013-02-28
申请号：US13592949
申请日：2012-08-23
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.
摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。
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13.发明授权公开(公告)号：US07745905B2
公开(公告)日：2010-06-29
申请号：US11683053
申请日：2007-03-07
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。
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公开(公告)号：US20080237787A1
公开(公告)日：2008-10-02
申请号：US11836609
申请日：2007-08-09
IPC分类号： H01L23/48
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse.The present invention is provided with a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. And a fuse wiring is cut by passing beyond a predetermined current value. A first electrode pad is connected to one side of a fuse wiring. A second electrode pad is connected to the other of a fuse wiring. A pollution-control layer is formed in the upper layer and the lower layer of a fuse wiring via an insulating layer. It is formed via an insulating layer to the side surface of a fuse wiring, it connects with a pollution-control layer, and the first via hole wiring of a pair surrounds a fuse wiring. To a fuse wiring, the second via hole wiring of a pair is formed in the outside of a first via hole wiring so that a first via hole wiring may be surrounded.
摘要翻译： 本发明的目的在于提供一种使用电熔丝进行可靠的浮雕处理的半导体集成电路。 本发明提供一种熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 并且通过超过预定电流值来切断熔丝布线。 第一电极焊盘连接到熔丝布线的一侧。 第二电极焊盘连接到熔丝布线中的另一个。 通过绝缘层在熔丝布线的上层和下层形成污染控制层。 它通过绝缘层形成在熔丝布线的侧面，它与污染控制层相连，一对第一通孔布线围绕熔丝布线。 对于熔丝布线，一对的第二通孔布线形成在第一通孔布线的外侧，使得可以包围第一通孔布线。
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公开(公告)号：US08681527B2
公开(公告)日：2014-03-25
申请号：US12938001
申请日：2010-11-02
申请人： Shigeki Obayashi
发明人： Shigeki Obayashi
IPC分类号： G11C17/14
摘要： To provide a semiconductor device capable of reducing the line width of a fuse.In the semiconductor device, a dummy fuse is provided adjacent to a fuse, each wiring width of the fuse and the dummy fuse is set to the minimum line width, and the interval between the fuse and the dummy fuse is set to the minimum interval. Consequently, the exposure condition of the fuse and the dummy fuse is optimized by OPC, and therefore, it is possible to form the fuse with the minimum line width.
摘要翻译： 提供能够减小保险丝的线路宽度的半导体器件。 在半导体装置中，与保险丝相邻设置虚拟熔丝，将熔丝和虚拟熔丝的各布线宽度设定为最小线宽，将熔丝和虚拟熔丝之间的间隔设定为最小间隔。 因此，保险丝和虚拟保险丝的曝光条件由OPC优化，因此可以形成具有最小线宽的保险丝。
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16.发明申请SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗公开(公告)号：US20110273952A1
公开(公告)日：2011-11-10
申请号：US13186769
申请日：2011-07-20
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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公开(公告)号：US20090179247A1
公开(公告)日：2009-07-16
申请号：US12354254
申请日：2009-01-15
申请人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
发明人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
CPC分类号： H01L21/823892 , H01L27/092
摘要： A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.
摘要翻译： 在具有三重阱结构的半导体器件中提供了可以提高制造成品率和产品可靠性的技术。 形成在浅p型阱中的n沟道型场效应晶体管和形成在浅n型阱中的p沟道型场效应晶体管并且对电路操作无贡献的逆变器电路设置在 在p型衬底中形成深n型阱; 使用第一层的布线将浅的p型阱连接到基板; 并且p沟道型场效应晶体管的栅电极和n沟道型场效应晶体管的栅电极使用最上层的布线连接到浅n型阱。
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公开(公告)号：US08558343B2
公开(公告)日：2013-10-15
申请号：US12718593
申请日：2010-03-05
申请人： Shigeki Obayashi
发明人： Shigeki Obayashi
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , G11C17/18 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a semiconductor device realizing reliable cutting of a fuse without enlarging layout area of a fuse element and the reduced number of wiring layers of a preventing wall that prevents diffusion of fuse copper atoms. A fuse is formed by using a wire in a metal wiring layer as an upper layer in a plurality of metal wiring layers. Wires are disposed just above and just below a fuse each with a gap of at least two wiring layers. In an upper layer, a power wire that transmits power supply voltage is used as a part covering a preventing wall structure just above the fuse.
摘要翻译： 本发明提供了一种半导体器件，其实现熔丝的可靠切割，而不会扩大熔丝元件的布局面积，并且减少了阻止熔丝铜原子扩散的防止壁的布线层数。 通过在多个金属布线层中的金属布线层中的导线作为上层形成熔丝。 电线布置在每个具有至少两个布线层的间隙的保险丝的正上方和正下方。 在上层，传输电源电压的电源线被用作覆盖保险丝正上方的预防壁结构的部分。
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公开(公告)号：US20090141569A1
公开(公告)日：2009-06-04
申请号：US12367871
申请日：2009-02-09
IPC分类号： G11C11/416 , G11C5/14 , G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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20.发明授权Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗公开(公告)号：US08630142B2
公开(公告)日：2014-01-14
申请号：US13492530
申请日：2012-06-08
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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