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    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110024847A1

    公开(公告)日：2011-02-03

    申请号：US12901858

    申请日：2010-10-11

    申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device 失效
    半导体集成电路装置及半导体集成电路装置的制造方法

    公开(公告)号：US08017464B2

    公开(公告)日：2011-09-13

    申请号：US12558498

    申请日：2009-09-12

    申请人： Masao Sugiyama ,  Yoshiyuki Kaneko ,  Yoshinori Kondo ,  Masayoshi Hirasawa

    发明人： Masao Sugiyama ,  Yoshiyuki Kaneko ,  Yoshinori Kondo ,  Masayoshi Hirasawa

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/28518 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    摘要： As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects.In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.

    摘要翻译： 作为构成前金属层间绝缘膜的方法，认为通过臭氧TEOS形成氧化硅膜的填充性良好的CVD硅氧化物类绝缘膜，在高温下回流以使其平坦化， 然后通过等离子体TEOS层叠具有良好CMP耐刮擦性的氧化硅膜，并且进一步通过CMP对其进行平坦化。 但是，在形成接触孔的工序中，在金属间绝缘膜的裂纹暴露在接触孔内，阻挡金属侵入其中而引起短路缺陷。 在本发明中，在预金属工艺中，在蚀刻停止膜上形成臭氧TEOS膜之后，臭氧TEOS膜被一次回蚀刻，以便在栅极结构上暴露蚀刻停止膜，之后， 在剩余的臭氧TEOS膜上形成等离子体TEOS膜，然后通过CMP平坦化等离子体TEOS膜。

    Method of manufacturing semiconductor device
    8.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06461946B2

    公开(公告)日：2002-10-08

    申请号：US09843859

    申请日：2001-04-30

    申请人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

    发明人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

    IPC分类号： H01L2104

    CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/76218 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892

    摘要： Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

    摘要翻译： 从多个方向注入P型和N型杂质。 将注入方向相对于半导体衬底的主表面的法线的倾斜角度θ固定为10°，将偏转角度phi设定为这样的四个方向（X，X + 90°，X + 180°， 在沿着半导体基板的主表面成直角交叉的两条线上投影指示注入方向的矢量的分量相对的X + 270°，其中X是任意角度）。 因此，抑制元件隔离的击穿电压对阱边界的方向的依赖性，以实现元件隔离在所有方向上的高击穿电压。

    Semiconductor device comprising a salicide structure
    9.
    发明授权
    Semiconductor device comprising a salicide structure 失效
    包括硅化物结构的半导体器件

    公开(公告)号：US5635746A

    公开(公告)日：1997-06-03

    申请号：US575194

    申请日：1995-12-20

    申请人： Masatoshi Kimura ,  Masao Sugiyama

    发明人： Masatoshi Kimura ,  Masao Sugiyama

    IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823835 ,  Y10S257/914

    摘要： After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

    摘要翻译： 在形成栅电极和源/漏区之后，使用抗蚀剂掩模将N离子或O离子注入到预定区域中，并且在衬底的整个表面上沉积Ti层，然后Ti层自身被硅化 通过热处理对准，由此在栅极电极和源极/漏极区域10上形成预定区域的高电阻率TixNySiz混合层，并且在另一个区域上形成低电阻率TiSi 2层12。