公开(公告)号：US20210271615A1

公开(公告)日：2021-09-02

申请号：US16999121

申请日：2020-08-21

Applicant: Kioxia Corporation

Inventor： Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME

IPC: G06F13/16

Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.

公开(公告)号：US20210082525A1

公开(公告)日：2021-03-18

申请号：US16807890

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro SUEMATSU ,  Masaru KOYANAGI ,  Kensuke YAMAMOTO ,  Ryo FUKUDA

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.

公开(公告)号：US20250021260A1

公开(公告)日：2025-01-16

申请号：US18899647

申请日：2024-09-27

Applicant: Kioxia Corporation

Inventor： Kensuke YAMAMOTO

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor memory device includes a memory cell storing data; a signal pad inputting write data to the memory cell and from which read data read from the memory cell is output to an external controller; a first control pad receiving a first timing control signal f from the external controller; and a second control pad outputting a second timing control signal to the external controller. In a first time period after a data out command is received, dummy data are output from the signal pad while the second timing control signal from the second control pad is toggling in response to toggling of the first timing control signal input to the first control pad. In a second time period after the first time period, read data are output from the signal pad while the second timing control signal is toggling in response to toggling of the first timing control signal.

公开(公告)号：US20230018613A1

公开(公告)日：2023-01-19

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US20220158639A1

公开(公告)日：2022-05-19

申请号：US17588702

申请日：2022-01-31

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: H03K19/0185 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

公开(公告)号：US20220137870A1

公开(公告)日：2022-05-05

申请号：US17575749

申请日：2022-01-14

Applicant: Kioxia Corporation

Inventor： Kensuke YAMAMOTO

IPC: G06F3/06

Abstract: A memory system outputs read enable signals RE and /RE during a period of a standby time tWHR2 necessary for a process of output to a controller, and causes an output, circuit to output dummy data preset in signals DQS and /DQS.

公开(公告)号：US20210174882A1

公开(公告)日：2021-06-10

申请号：US17017726

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Yousuke HAGIWARA ,  Kensuke YAMAMOTO ,  Takeshi HIOKA ,  Satoshi INOUE

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

公开(公告)号：US20200036561A1

公开(公告)日：2020-01-30

申请号：US16590191

申请日：2019-10-01

Applicant: KIOXIA Corporation

Inventor： Kensuke YAMAMOTO ,  Kosuke YANAGIDAIRA

IPC: H04L25/02 ,  G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/16 ,  G11C11/409 ,  H03K19/00 ,  H03K19/177

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.