公开(公告)号：US20230023666A1

公开(公告)日：2023-01-26

申请号：US17961950

申请日：2022-10-07

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20220077089A1

公开(公告)日：2022-03-10

申请号：US17203990

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Shinya WATANABE ,  Shinya ARAI

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor storage device includes a first chip and a second chip. The first chip includes a first substrate, a transistor, and a first pad. The second chip includes a second pad, a memory cell array, and a second substrate. The second pad is on the first pad. The second chip is bonded to the first chip. The first chip and the second chip includes, when viewed in a first direction orthogonal to the first substrate, a first region and a second region. The first region includes the memory cell array. The second region surrounds an area around the first region and includes a wall extending from the first substrate to the second substrate. The second substrate includes a first opening passing through the second substrate in the second region.

公开(公告)号：US20210265314A1

公开(公告)日：2021-08-26

申请号：US17007719

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/544 ,  H01L21/50

Abstract: A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

公开(公告)号：US20250120083A1

公开(公告)日：2025-04-10

申请号：US18984875

申请日：2024-12-17

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20240397721A1

公开(公告)日：2024-11-28

申请号：US18797474

申请日：2024-08-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20230320107A1

公开(公告)日：2023-10-05

申请号：US18330779

申请日：2023-06-07

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA ,  Akira MINO ,  Masayoshi TAGAMI ,  Shinya ARAI

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  G11C16/0483 ,  G11C16/26 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

公开(公告)号：US20230075993A1

公开(公告)日：2023-03-09

申请号：US17643263

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Koichi SAKATA ,  Shinya ARAI ,  Susumu HASHIMOTO ,  Akira MINO ,  Shunsuke OKADA ,  Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a first conductive layer, and a second conductive layer arranged in this order in a first direction and separated from each other, a first semiconductor film extending in the first direction, intersecting the first conductive layer, and being in contact with the second conductive layer, and a first charge storage film arranged between the first semiconductor film and the first conductive layer, and being in contact with the second conductive layer, wherein the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer.

公开(公告)号：US20220406811A1

公开(公告)日：2022-12-22

申请号：US17683605

申请日：2022-03-01

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor storage device includes a stack, a columnar body, and a second conductive layer. The stack includes a plurality of first conductive layers and a plurality of insulating layers. In the stack, the plurality of first conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The second conductive layer is connected to the columnar body. The columnar body includes an insulating core, a memory film, and a semiconductor channel. The memory film is provided between the plurality of first conductive layers and the insulating core. The semiconductor channel is provided between the insulating core and the memory film. An upper surface of the insulating core is located lower than an upper end of the columnar body. The second conductive layer has a main body portion and a protrusion. The protrusion protrudes from the main body portion toward the upper surface of the insulating core, and extends in the first direction within the columnar body. The protrusion is in contact with the semiconductor channel on a bottom surface or a side surface of the protrusion.

公开(公告)号：US20240404920A1

公开(公告)日：2024-12-05

申请号：US18807170

申请日：2024-08-16

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20240147725A1

公开(公告)日：2024-05-02

申请号：US18408864

申请日：2024-01-10

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H10B43/27 ,  G11C16/14 ,  H01L21/764 ,  H01L29/06 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  G11C16/14 ,  H01L21/764 ,  H01L29/0649 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  G11C16/0483

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.