公开(公告)号：US20220302152A1

公开(公告)日：2022-09-22

申请号：US17475014

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Koichi SAKATA ,  Junichi SHIBATA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528

Abstract: In one embodiment, a semiconductor device includes first electrode layers spaced from one another in a first direction, and second electrode layers provided above the first electrode layers, and spaced from one another in the first direction. The device further includes a first columnar portion extending in the first direction in the first electrode layers, and including a first semiconductor layer, and a second columnar portion provided on the first columnar portion, extending in the first direction in the second electrode layers, and including a second semiconductor layer. The first columnar portion includes a first portion having a first width, and a second portion having a second width larger than the first width above the first portion. The second columnar portion includes a third portion having a third width, and a fourth portion having a fourth width larger than the third width above the third portion.

公开(公告)号：US20230075993A1

公开(公告)日：2023-03-09

申请号：US17643263

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Koichi SAKATA ,  Shinya ARAI ,  Susumu HASHIMOTO ,  Akira MINO ,  Shunsuke OKADA ,  Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a first conductive layer, and a second conductive layer arranged in this order in a first direction and separated from each other, a first semiconductor film extending in the first direction, intersecting the first conductive layer, and being in contact with the second conductive layer, and a first charge storage film arranged between the first semiconductor film and the first conductive layer, and being in contact with the second conductive layer, wherein the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer.

公开(公告)号：US20240315024A1

公开(公告)日：2024-09-19

申请号：US18595092

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Kazushi HARA ,  Yefei HAN ,  Keisuke NAKATSUKA ,  Koichi SAKATA

IPC: H10B43/27 ,  H01L25/00 ,  H01L25/065 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L25/50 ,  H10B43/35 ,  H01L25/0657

Abstract: In one embodiment, a semiconductor device includes a stacked film including electrode layers and first insulators alternately in a first direction, a top layer of the stacked film being a second insulator that is one of the first insulators. The device further includes a columnar portion including a third insulator, a charge storage layer, a fourth insulator and a first semiconductor layer that are sequentially provided in the stacked film. The device further includes a metal layer provided on the stacked film and the columnar portion, electrically connected to the first semiconductor layer, and including one or more layers. An upper end of the columnar portion is provided at a height between upper and lower faces of the second insulator. A lower end of a highest layer among the one or more layers is provided at a position lower than the upper face of the second insulator.

公开(公告)号：US20240292619A1

公开(公告)日：2024-08-29

申请号：US18586775

申请日：2024-02-26

Applicant: Kioxia Corporation

Inventor： Yasuaki NAKATA ,  Masayoshi TAGAMI ,  Koichi SAKATA ,  Miki TOSHIMA

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes transistors disposed on a substrate; a first metal wiring layer disposed over the transistors at a first position, the first metal wiring layer including a first metal wiring; a stacked body, disposed above the first metal wiring layer, including a first conductive layers and first insulating layers alternately stacked; a pillar including a semiconductor layer that includes a first type impurity in an upper end and penetrates through the stacked body; and a second conductive layer disposed at a second position further from the substrate than the first position, overlapped with the first metal wiring or another metal wiring in the first metal wiring layer, and not electrically connected to any of the transistors, the first conductive layers, or the first metal wiring layer. The second conductive layer has a higher melting point than the first metal wiring.

公开(公告)号：US20240315037A1

公开(公告)日：2024-09-19

申请号：US18599586

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Keita HASEGAWA ,  Keisuke NAKATSUKA ,  Koichi SAKATA

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H01L2225/06541

Abstract: A semiconductor device includes a first chip including a peripheral circuit, and a second chip bonded to the first chip. The second chip includes a stacked body, a contact, a first column-shaped part, a second conductive layer, and a second column-shaped part. The contact is connected to a staircase part of the stacked body. The first column-shaped part is formed to extend through a memory part of the stacked body in a first direction and forms a memory cell transistor at an intersection part with a first conductive layer. The second conductive layer is formed above the stacked body and connected to an upper end part of the first column-shaped part. The second column-shaped part is formed to extend through the staircase part in the first direction. The second column-shaped part is electrically insulated from the second conductive layer.

公开(公告)号：US20250107085A1

公开(公告)日：2025-03-27

申请号：US18602979

申请日：2024-03-12

Applicant: Kioxia Corporation

Inventor： Shota KASHIYAMA ,  Koichi SAKATA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

Abstract: First conductors and first insulators are alternately arranged one by one in a first direction in a first region. The first insulators and second insulators are alternately arranged one by one in the first direction in a second region. The memory pillar penetrates the first conductors and the first insulators in the first region and includes a semiconductor. A second conductor includes first to third portions. The second portion electrically couples the first portion and the third portion. A side surface of the third portion is electrically coupled to the semiconductor. A first film extends along the first direction in the second region. A second film contacts the first film, extends along the first direction, and includes carbon or metal. One of the second insulators includes a portion extending along the first and second films in the second region and being distanced from the second film.

公开(公告)号：US20230017218A1

公开(公告)日：2023-01-19

申请号：US17952718

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/762

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.