公开(公告)号：US20100117116A1

公开(公告)日：2010-05-13

申请号：US12690778

申请日：2010-01-20

申请人： Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

发明人： Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

IPC分类号： H01L29/87

CPC分类号： H01L29/7436 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/87 ,  H01L2924/0002 ,  Y10S438/919 ,  Y10S438/922 ,  Y10S438/923 ,  H01L2924/00

摘要： An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

公开(公告)号：US20090283810A1

公开(公告)日：2009-11-19

申请号：US12511845

申请日：2009-07-29

申请人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

发明人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

IPC分类号： H01L29/94 ,  H03K3/01

CPC分类号： H01L29/94 ,  H01L27/0811

摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

摘要翻译： 公开了一种在n型阱中包括电容器的电路装置。 电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。 任选地存在的辅助掺杂层确保电容器的高面积电容，尽管具有高的ESD强度。

公开(公告)号：US07279726B2

公开(公告)日：2007-10-09

申请号：US11411403

申请日：2006-04-26

申请人： Kai Esmark ,  Ulrich Glaser ,  Martin Streibl

发明人： Kai Esmark ,  Ulrich Glaser ,  Martin Streibl

IPC分类号： H01L29/00 ,  H02H3/22

CPC分类号： H01L27/0255

摘要： An ESD protection device for protecting a circuit against electrostatic discharges. The ESD protection device having a series circuit of N diodes, each diode comprising an anode and a cathode. The series circuit being connected between two supply potentials. The diodes being so arranged that a spatial distance between the anode of a first diode and the cathode of an Nth diode of the series circuit is less than a maximum distance between the anode or cathode of a first spatially outer diode of the series circuit and the anode or cathode of a second spatially outer diode of the series circuit.

摘要翻译： 一种用于保护电路免受静电放电的ESD保护装置。 该ESD保护装置具有N个二极管的串联电路，每个二极管包括阳极和阴极。 串联电路连接在两个电源之间。 二极管被布置成使得第一二极管的阳极与串联电路的第N个二极管的阴极之间的空间距离小于串联电路的第一空间外部二极管的阳极或阴极之间的最大距离， 串联电路的第二空间外部二极管的阳极或阴极。

公开(公告)号：US07202527B2

公开(公告)日：2007-04-10

申请号：US10903027

申请日：2004-07-29

申请人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

发明人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/7833 ,  H01L29/7836

摘要： A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.

摘要翻译： MOS晶体管包括漏极区，源极区和栅电极。 第一导电类型的掺杂原子通过至少两个另外的注入步骤注入到漏区和源区的区域中，使得漏区和衬底区之间的pn结垂直移位，MOS的电压比 可以设置横向击穿电压和垂直击穿电压之间的晶体管。

公开(公告)号：US06905892B2

公开(公告)日：2005-06-14

申请号：US10200067

申请日：2002-07-19

申请人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  G01R31/26

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

摘要翻译： 本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大 具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。

公开(公告)号：US08076728B2

公开(公告)日：2011-12-13

申请号：US12511845

申请日：2009-07-29

申请人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

发明人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

IPC分类号： H01L23/62

CPC分类号： H01L29/94 ,  H01L27/0811

摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

摘要翻译： 公开了一种在n型阱中包括电容器的电路装置。 电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。 任选地存在的辅助掺杂层确保了电容器的高面积电容，尽管高度的ESD强度。

公开(公告)号：US07359169B2

公开(公告)日：2008-04-15

申请号：US10536176

申请日：2003-11-24

申请人： Kai Esmark ,  Harald Gossner ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Kai Esmark ,  Harald Gossner ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H02H9/00 ,  H02H9/08 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC分类号： H02H9/046

摘要： A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.

摘要翻译： 描述了保护集成电路免受静电放电或电过压的电路。 电路装置具有在集成电路的连接和电源电压之间串联连接的第一和第二保护元件。 当发生静电放电或电过压时，电流流过形成在第一和第二保护元件上的导电路径。 包含电路元件的电流路径限制通过第一保护元件的电流与第一保护元件并联连接。 当不产生静电放电或电过度应力时，第一保护元件具有阻塞行为，有限的电流流过电流通路和第二保护元件。

公开(公告)号：US20050263817A1

公开(公告)日：2005-12-01

申请号：US11138918

申请日：2005-05-26

申请人： Martin Wendel ,  Martin Streibl ,  Kai Esmark ,  Philipp Riess ,  Thomas Schafbauer

发明人： Martin Wendel ,  Martin Streibl ,  Kai Esmark ,  Philipp Riess ,  Thomas Schafbauer

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/78

摘要： A transistor contains a source region and a drain region. Two or more fill areas are formed such that the fill areas and the source and/or drain region engage in one another. The fill areas have vertical dimensions which are at least of equal size to the vertical dimensions of the source and/or of the drain region. The fill areas and the source and/or drain region extend at least partially over a common vertical section. The fill areas are formed from an oxide and/or a nitride.

摘要翻译： 晶体管包含源极区和漏极区。 形成两个或更多个填充区域，使得填充区域和源极和/或漏极区域彼此接合。 填充区具有与源极和/或漏极区域的垂直尺寸至少相等的垂直尺寸。 填充区域和源极和/或漏极区域至少部分地延伸在共同的垂直部分上。 填充区域由氧化物和/或氮化物形成。

公开(公告)号：US06930501B2

公开(公告)日：2005-08-16

申请号：US10866863

申请日：2004-06-14

申请人： Silke Bargstädt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Silke Bargstädt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L23/544 ,  H01L23/60 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

公开(公告)号：US06884688B2

公开(公告)日：2005-04-26

申请号：US10263097

申请日：2002-10-02

申请人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

发明人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/7833 ,  H01L29/7836

摘要： A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.

摘要翻译： MOS晶体管包括漏极区，源极区和栅电极。 第一导电类型的掺杂原子通过至少两个另外的注入步骤注入到漏区和源区的区域中，使得漏区和衬底区之间的pn结垂直移位，MOS的电压比 可以设置横向击穿电压和垂直击穿电压之间的晶体管。