公开(公告)号：US20050146974A1

公开(公告)日：2005-07-07

申请号：US10749690

申请日：2003-12-30

Applicant: John Halbert ,  Robert Ellis ,  Kuljit Bains ,  Chris Freeman

Inventor： John Halbert ,  Robert Ellis ,  Kuljit Bains ,  Chris Freeman

IPC: G06F12/08 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4094 ,  G11C8/00

CPC classification number: G11C11/4094 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C2207/005 ,  Y02D10/13

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

Abstract translation: 提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问写入数据 通过写入操作指向至少一行，使得数据直接从存储单元行写入读出放大器行，并存储由读出放大器行缓冲的数据变脏的指示。

公开(公告)号：US20050108469A1

公开(公告)日：2005-05-19

申请号：US10713784

申请日：2003-11-13

Applicant: Chris Freeman ,  Pete Vogt ,  Kuljit Bains ,  Robert Ellis ,  John Halbert ,  Michael Williams

Inventor： Chris Freeman ,  Pete Vogt ,  Kuljit Bains ,  Robert Ellis ,  John Halbert ,  Michael Williams

IPC: G06F13/16 ,  G06F12/00

CPC classification number: G06F13/16

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract translation: 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。 缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作 。 例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。 描述和要求保护其他实施例。

公开(公告)号：US07404055B2

公开(公告)日：2008-07-22

申请号：US11392471

申请日：2006-03-28

Applicant: Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

IPC: G06F12/00

CPC classification number: G06F13/1678

Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器 具有第二宽度的第二格式，其中临界部分包括在第一帧中。 关键部分可以包括在存储器设备等级上映射的高速缓存线。 描述和要求保护其他实施例。

公开(公告)号：US20070130374A1

公开(公告)日：2007-06-07

申请号：US11280837

申请日：2005-11-15

Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

IPC: G06F3/00

CPC classification number: G06F13/1694

Abstract: In some embodiments, a chip includes memory banks and data ports, including at least first and second data ports, coupled to the memory banks. The chip also includes control circuitry to control a configuration of the first data port to be in one of multiple configurations in response to a configuration command, wherein the available configurations for the first data port include at least two of the following: whether the first data port (1) may only be used for read transactions, (2) may only be used for write transactions, or (3) may be used for either read or write transactions while in the configuration. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括耦合到存储体的存储器组和数据端口，包括至少第一和第二数据端口。 该芯片还包括控制电路，用于响应于配置命令将第一数据端口的配置控制为多个配置之一，其中第一数据端口的可用配置包括以下中的至少两个：第一数据 端口（1）只能用于读取事务，（2）只能用于写入事务，或者（3）可以在配置中用于读取或写入事务。 描述其他实施例。

公开(公告)号：US20050259480A1

公开(公告)日：2005-11-24

申请号：US11192249

申请日：2005-07-27

Applicant: Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  David Zimmerman

Inventor： Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  David Zimmerman

IPC: G11C5/00 ,  G11C29/48 ,  G11C29/56

CPC classification number: G11C29/48 ,  G11C29/56 ,  G11C2029/5602

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract translation: 本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。 一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。 在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。 其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。 在权利要求中描述了其它实施例。

公开(公告)号：US20130272049A1

公开(公告)日：2013-10-17

申请号：US13997148

申请日：2011-12-02

Applicant: Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: G11C5/06 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract translation: 用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

公开(公告)号：US20070223264A1

公开(公告)日：2007-09-27

申请号：US11388464

申请日：2006-03-24

Applicant: Kuljit S. Bains ,  John Halbert

Inventor： Kuljit S. Bains ,  John Halbert

IPC: G11C5/06

CPC classification number: G11C8/12

Abstract: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括至少四组存储器组和至少四组输出导体，其中每组输出导体对应于存储器组组中的不同组。 芯片还包括通过将存储器组中的每一组的至少一个存储体的读取数据提供给其对应的输出导体组来执行读取操作的电路。 描述其他实施例。

公开(公告)号：US20080056047A1

公开(公告)日：2008-03-06

申请号：US11932470

申请日：2007-10-31

Applicant: Sandeep Jain ,  Animesh Mishra ,  John Halbert

Inventor： Sandeep Jain ,  Animesh Mishra ,  John Halbert

IPC: G11C7/00

CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622

Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Abstract translation: 一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数 ，从而减少刷新期间消耗的功率量。

公开(公告)号：US20070211548A1

公开(公告)日：2007-09-13

申请号：US11801909

申请日：2007-05-10

Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3089 ,  G11C5/04 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1063

Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Abstract translation: 确定存储器模块的多个设备的温度。 在一个示例中，存储器模块包括印刷电路板，印刷电路板上的多个存储器芯片，每个芯片包含多个存储单元和热传感器，以及印刷电路板上的多路复用器，独立于存储器芯片 ，耦合到每个热传感器。 电流源耦合到多路复用器以向每个热传感器提供电流，并且电压检测器耦合到多路复用器以在施加电流时检测来自每个热传感器的电压。 温度电路耦合到电压检测器，以基于检测到的电压来确定每个存储器芯片的温度。

公开(公告)号：US06530006B1

公开(公告)日：2003-03-04

申请号：US09664982

申请日：2000-09-18

Applicant: James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

Inventor： James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

IPC: G06F1200

CPC classification number: G06F13/4239

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

Abstract translation: 本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。 该系统包括存储器件，存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。 存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。 缓冲器互连存储器件和存储器控制器。 时钟电路嵌入到addr / cmd缓冲区中。 时钟电路接收输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟偏移。