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    System and method for providing a non-power-of-two burst length in a memory system
    13.
    发明授权
    System and method for providing a non-power-of-two burst length in a memory system 有权
    在存储器系统中提供非二次突发长度的系统和方法

    公开(公告)号：US08023358B2

    公开(公告)日：2011-09-20

    申请号：US12061045

    申请日：2008-04-02

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

    IPC分类号： G11C8/00

    CPC分类号： G11C5/00 ,  G11C7/1018

    摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

    摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

    System for providing on-die termination of a control signal bus
    14.
    发明授权
    System for providing on-die termination of a control signal bus 有权
    用于提供控制信号总线的管芯端接的系统

    公开(公告)号：US07952944B2

    公开(公告)日：2011-05-31

    申请号：US12112391

    申请日：2008-04-30

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1048 ,  G11C7/109 ,  H04L25/0298

    摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.

    摘要翻译： 一种用于提供控制信号总线的管芯端接（ODT）的系统。 该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。 该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。 该数据用于设置由ODT提供的终端电阻的电平。

    Synchronous memory having shared CRC and strobe pin
    15.
    发明授权
    Synchronous memory having shared CRC and strobe pin 失效
    具有共享CRC和选通引脚的同步存储器

    公开(公告)号：US07636262B2

    公开(公告)日：2009-12-22

    申请号：US11923691

    申请日：2007-10-25

    申请人： Kyu-Hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-Hyoun Kim ,  Paul W. Coteus

    IPC分类号： G11C7/10

    CPC分类号： G06F13/1689 ,  G06F11/1004

    摘要： A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.

    摘要翻译： 具有存储元件芯片（DRAM）的存储器系统和具有用于传送数据的多个驱动器和接收器以及锁存器的存储器控​​制器芯片。 对于写时钟，写入数据和写入CRC（循环冗余校验）从存储器控制器传送到DRAM，并锁存进行错误检查。 读取被计时，并且读取的数据被接收并被传送到读取数据锁存器，同时还接收用于从DRAM确认数据完整性的时钟读选通脉冲。 每个芯片都有一个双功能引脚，在写入期间充当共享的CRC引脚，并在读取期间充当共享的选通引脚。 具有CRC信号和DQS信号的数据传输通过两个路径CRC0 / DQS和CRC1 / DQS1传送。 也可以通过CRC0 / DQS信号在一个路径上传送CRC信号。 读操作没有CRC，并且不需要CRC，因为可以通过存储器纠错编码（ECC）来检测读取期间的传输错误。 写入数据将源同步I / O数据提供给调制解调器高速存储器通信所需的所述存储器元件芯片。

    SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS
    16.
    发明申请
    SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS 有权
    用于提供控制信号总线接线端子的系统

    公开(公告)号：US20090273960A1

    公开(公告)日：2009-11-05

    申请号：US12112391

    申请日：2008-04-30

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： G11C5/02 ,  G11C7/00 ,  H03K19/003

    CPC分类号： G11C7/1078 ,  G11C7/1048 ,  G11C7/109 ,  H04L25/0298

    摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.

    摘要翻译： 一种用于提供控制信号总线的管芯端接（ODT）的系统。 该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。 该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。 该数据用于设置由ODT提供的终端电阻的电平。

    System for providing open-loop quadrature clock generation
    17.
    发明授权
    System for providing open-loop quadrature clock generation 失效
    提供开环正交时钟生成系统

    公开(公告)号：US07612621B2

    公开(公告)日：2009-11-03

    申请号：US11749409

    申请日：2007-05-16

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

    IPC分类号： H03B27/00

    CPC分类号： H03K5/151 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00234

    摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

    摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

    SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN
    18.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN 有权
    用于提供具有共享错误反馈PIN的存储器件的系统和方法

    公开(公告)号：US20090187794A1

    公开(公告)日：2009-07-23

    申请号：US12018030

    申请日：2008-01-22

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1004

    摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

    摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

    MEMORY DEVICE REFRESH
    19.
    发明申请
    MEMORY DEVICE REFRESH 有权
    存储设备刷新

    公开(公告)号：US20140071778A1

    公开(公告)日：2014-03-13

    申请号：US13609655

    申请日：2012-09-11

    申请人： Paul W. Coteus ,  Douglas J. Joseph ,  Kyu-hyoun Kim

    发明人： Paul W. Coteus ,  Douglas J. Joseph ,  Kyu-hyoun Kim

    IPC分类号： G11C11/402

    CPC分类号： G11C11/40611 ,  G06F13/1668 ,  Y02D10/14

    摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.

    摘要翻译： 根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。 基于接收到同步命令，内存刷新定时器在存储器设备内复位。 基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。 基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

    Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device
    20.
    发明授权
    Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device 有权
    实现垂直管芯堆叠，在多晶硅通孔堆叠半导体器件中分配多个管芯的逻辑功能

    公开(公告)号：US08516409B2

    公开(公告)日：2013-08-20

    申请号：US12944020

    申请日：2010-11-11

    申请人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

    发明人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

    IPC分类号： G06F17/50

    CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C17/143 ,  G11C17/16 ,  G11C29/12 ,  G11C29/785 ,  G11C29/802 ,  G11C2229/763 ,  G11C2229/766 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

    摘要： A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.

    摘要翻译： 一种用于实现芯片堆叠以在多个裸片上分布逻辑功能的方法和电路，以及提供了通过硅片通过堆叠的半导体器件的裸片识别和备用，以及设置有被摄体电路的设计结构。 管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。 在每个相应的管芯中执行相应的预定义功能，并且将相应的功能结果提供给管芯堆叠中的相邻管芯。 管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。 通过组合每个管芯上的多个选择的信号来形成操作管芯签名。 使用TSV互连将芯片签名耦合到下一级相邻裸片，其中它与该芯片签名组合。