公开(公告)号：US07692213B2

公开(公告)日：2010-04-06

申请号：US11835059

申请日：2007-08-07

申请人： Lee Wee Teo ,  Yung Fu Chong ,  Elgin Kiok Boone Quek ,  Alain Chan

发明人： Lee Wee Teo ,  Yung Fu Chong ,  Elgin Kiok Boone Quek ,  Alain Chan

IPC分类号： H01L29/778

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

摘要翻译： 一种集成电路系统，包括：提供包括PFET栅极和PFET栅极电介质的PFET器件; 从与第一PFET栅极侧壁间隔物对准的第一外延层形成源极/漏极延伸; 以及从与第二PFET栅极侧壁间隔物对准的第二外延层形成源极/漏极。

公开(公告)号：US07795104B2

公开(公告)日：2010-09-14

申请号：US12030598

申请日：2008-02-13

申请人： Elgin Kiok Boone Quek ,  Lee Wee Teo ,  Shyue Seng Tan

发明人： Elgin Kiok Boone Quek ,  Lee Wee Teo ,  Shyue Seng Tan

IPC分类号： H01L21/20

CPC分类号： H01L29/66166 ,  H01L21/324 ,  H01L27/0802 ,  H01L28/20

摘要： A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing characteristics, such that upon irradiating the device structure, the radiation absorbing layer attenuates the intensity of the radiation so that a variation in dopant activation takes place within the device structure. Accordingly, device structures are formed having a variation in electrical resistance independent of the physical size of the device structures.

摘要翻译： 用于形成具有导电性变化的器件结构的方法包括形成器件结构和覆盖器件结构的辐射吸收层。 辐射吸收层具有空间变化和辐射吸收特性，使得在照射器件结构时，辐射吸收层衰减辐射的强度，使得在器件结构内发生掺杂剂激活的变化。 因此，形成具有独立于器件结构的物理尺寸的电阻变化的器件结构。

公开(公告)号：US20090203185A1

公开(公告)日：2009-08-13

申请号：US12030598

申请日：2008-02-13

申请人： Elgin Kiok Boone Quek ,  Lee Wee Teo ,  Shyue Seng Tan

发明人： Elgin Kiok Boone Quek ,  Lee Wee Teo ,  Shyue Seng Tan

IPC分类号： H01L21/20 ,  H01L21/02

CPC分类号： H01L29/66166 ,  H01L21/324 ,  H01L27/0802 ,  H01L28/20

摘要： A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing characteristics, such that upon irradiating the device structure, the radiation absorbing layer attenuates the intensity of the radiation so that a variation in dopant activation takes place within the device structure. Accordingly, device structures are formed having a variation in electrical resistance independent of the physical size of the device structures.

摘要翻译： 用于形成具有导电性变化的器件结构的方法包括形成器件结构和覆盖器件结构的辐射吸收层。 辐射吸收层具有空间变化和辐射吸收特性，使得在照射器件结构时，辐射吸收层衰减辐射的强度，使得在器件结构内发生掺杂剂激活的变化。 因此，形成具有独立于器件结构的物理尺寸的电阻变化的器件结构。

公开(公告)号：US07998835B2

公开(公告)日：2011-08-16

申请号：US12008841

申请日：2008-01-15

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

公开(公告)号：US20100258868A1

公开(公告)日：2010-10-14

申请号：US12422694

申请日：2009-04-13

申请人： Chunshan Yin ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee

发明人： Chunshan Yin ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78621

摘要： A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.

摘要翻译： 一种制造集成电路系统的方法包括：在第一层和第三层之间提供第二层; 在第三层上形成有源器件; 形成第三层以在有源器件下方形成岛状区域; 形成第二层以形成在岛区下方具有底切的浮动第二层; 以及围绕岛区域和浮动第二层沉积第四层。

公开(公告)号：US07846800B2

公开(公告)日：2010-12-07

申请号：US12043148

申请日：2008-03-06

申请人： Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

发明人： Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L27/0251 ,  H01L27/092

摘要： A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.

摘要翻译： 提供具有电路控制端子，初级电路和保护电路的电路。 初级电路包括厚度T1的初级控制端子和主栅极氧化物。 主控制端子耦合到电路控制端子。 具有保护控制端子的保护电路耦合到初级电路。 保护电路包括小于T1的第二厚度T2的保护栅极氧化物。 保护栅极氧化物减少了初级电路中的等离子体引起的损坏。

公开(公告)号：US20090179226A1

公开(公告)日：2009-07-16

申请号：US12008841

申请日：2008-01-15

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L21/30 ,  H01L29/12

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

公开(公告)号：US08530310B2

公开(公告)日：2013-09-10

申请号：US12650561

申请日：2009-12-31

申请人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

发明人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

摘要翻译： 提出了一种形成装置的方法。 提供了具有具有第一和第二相邻表面的特征的基底。 器件层形成在特征的第一和第二相邻表面上。 第一相邻表面上的器件层的第一部分包括纳米晶体，而第二相邻表面上的器件层的第二部分没有纳米晶体。

公开(公告)号：US08242559B2

公开(公告)日：2012-08-14

申请号：US12422694

申请日：2009-04-13

申请人： Chunshan Yin ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee

发明人： Chunshan Yin ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78621

摘要： A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.

摘要翻译： 一种制造集成电路系统的方法包括：在第一层和第三层之间提供第二层; 在第三层上形成有源器件; 形成第三层以在有源器件下方形成岛状区域; 形成第二层以形成在岛区下方具有底切的浮动第二层; 以及围绕岛区域和浮动第二层沉积第四层。

公开(公告)号：US20110278645A1

公开(公告)日：2011-11-17

申请号：US13191288

申请日：2011-07-26

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L29/165

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。