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公开(公告)号：US5278464A
公开(公告)日：1994-01-11
申请号：US892834
申请日：1992-06-02
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/0136 , H03K19/086
摘要： A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a logic high to a logic low. The current source (16) is deactivated for a predetermined time delay after the input signal (Vi) switches from a logic high to a logic low.
摘要翻译： 电流驱动器电路（10）响应于逻辑高的输入信号（VI）将电流供给到输出节点（N4）。 当前的驱动器电路（10）利用电流源（16），其响应于从逻辑高电平切换到逻辑低电平的输入信号（VI），从电流源输出来自输出节点（N4）的电流。 在输入信号（Vi）从逻辑高电平切换到逻辑低电平之后，电流源（16）被停用预定的时间延迟。
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公开(公告)号：US4806799A
公开(公告)日：1989-02-21
申请号：US160885
申请日：1988-02-26
申请人： Perry H. Pelley, III , Ruey J. Yu , Scott G. Nogle
发明人： Perry H. Pelley, III , Ruey J. Yu , Scott G. Nogle
IPC分类号： H03K17/567 , H03K3/021 , H03K3/356 , H03K19/0175 , H03K19/092 , H03K17/10 , H03K19/003 , H03K19/086
CPC分类号： H03K19/017527 , H03K3/021 , H03K3/356017
摘要： In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.
摘要翻译： 在包括ECL和CMOS电路的集成电路中，有一个ECL到CMOS转换器，它将ECL逻辑电平转换为CMOS逻辑电平。 为了将ECL转换为CMOS电平，ECL逻辑高电平耦合到提供CMOS逻辑电平的NPN晶体管的基极。 防止ECL逻辑低电平耦合到NPN晶体管的基极。 通过类似的第二电路获得CMOS逻辑高电平，该第二电路响应于其输出耦合到P沟道晶体管的互补ECL信号。 P沟道晶体管提供CMOS逻辑高输出或不导通。
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公开(公告)号：US4791615A
公开(公告)日：1988-12-13
申请号：US944099
申请日：1986-12-22
CPC分类号： G11C29/83 , G11C29/844 , G11C8/12
摘要： A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row is provided to replace a defective row from the main array. A programmable redundant decoder is programmable to select the redundant row in response to the predecoder signals which select the defective row.
摘要翻译： 存储器具有地址缓冲器，其接收行地址和列地址，并将这些缓冲的地址信号输出到预解码器。 行解码器和列解码器使用由预解码器提供的预解码信号来从主阵列中选择行和列。 提供冗余行来替换主阵列中的有缺陷的行。 可编程冗余解码器是可编程的，以响应于选择缺陷行的预解码器信号来选择冗余行。
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公开(公告)号：US4740921A
公开(公告)日：1988-04-26
申请号：US784450
申请日：1985-10-04
IPC分类号： G11C11/409 , G11C11/4094 , G11C11/4096 , G11C11/34 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/4096
摘要： A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when the inputs are at a voltage intermediate a power supply voltage. Prior to the pair of bit lines being coupled to the data line pair, the data lines are biased to the intermediate voltage which is in the range of maximum gain of the secondary amplifier so that the secondary amplifier will operate at maximum gain which results in increased speed of operation of the dynamic random access memory.
摘要翻译： 动态随机存取存储器具有数据线对，其从选定的位线对接收数据。 耦合到数据线对的是用于放大从位线对提供给数据线对的数据的次级放大器。 当输入处于电源电压以上的电压时，次级放大器具有最大增益。 在一对位线耦合到数据线对之前，数据线被偏置到在次级放大器的最大增益范围内的中间电压，使得次级放大器将以最大增益工作，这导致增加 动态随机存取存储器的运行速度。
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公开(公告)号：US07564738B2
公开(公告)日：2009-07-21
申请号：US11464129
申请日：2006-08-11
IPC分类号： G11C8/16
CPC分类号： G11C8/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18
摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.
摘要翻译： 双速率存储器具有以行和列排列的单个字线存储单元阵列。 单个字线存储单元通过第一端口提供和存储数据。 寻址和控制电路耦合到单个字线存储单元的阵列。 寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。 边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。 存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。 在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。
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公开(公告)号：US20080037357A1
公开(公告)日：2008-02-14
申请号：US11464129
申请日：2006-08-11
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18
摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.
摘要翻译： 双速率存储器具有以行和列排列的单个字线存储单元阵列。 单个字线存储单元通过第一端口提供和存储数据。 寻址和控制电路耦合到单个字线存储单元的阵列。 寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。 边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。 存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。 在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。
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公开(公告)号：US06169420A
公开(公告)日：2001-01-02
申请号：US09131515
申请日：1998-08-10
IPC分类号： H03K190175
CPC分类号： H03K19/00315
摘要： An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.
摘要翻译： 一种具有保护电路（228,230,232）的输出缓冲器（200），其响应于输出引脚（202）上的外部电压来调节对输出驱动电路（224,226）的控制。 当输出引脚处于三态状态并接收超出预定电压范围的外部电压时，保护电路调节输出驱动电路中的晶体管（224）的控制栅上的电压。 保护电路将晶体管两端的电压保持在晶体管的容限内。 在一个实施例中，输出驱动电路具有上拉（204）和下拉（206）部分。 输出缓冲器提供具有低电压器件的高电压输出驱动器。
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公开(公告)号：US5760626A
公开(公告)日：1998-06-02
申请号：US626703
申请日：1996-04-01
申请人： Perry H. Pelley, III
发明人： Perry H. Pelley, III
摘要： A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data value to the receiver (40) after the data value is no longer present on the bus (50). The data latch (10) has a data storage circuit (11), a diode clamping circuit (12), and a current sourcing circuit (13). The data value is stored by the data storage circuit (11) by a feed-back loop circuit.
摘要翻译： 数据值从总线（50）传递到接收器（40）而没有传播延迟。 数据锁存器（10）在总线（50）正在生成数据值的同时存储数据值。 数据锁存器（10）然后保存数据值，并且在数据值不再存在于总线（50）上之后将数据值提供给接收器（40）。 数据锁存器（10）具有数据存储电路（11），二极管钳位电路（12）和电流源电路（13）。 数据值由数据存储电路（11）由反馈回路电路存储。
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公开(公告)号：US5323360A
公开(公告)日：1994-06-21
申请号：US55596
申请日：1993-05-03
申请人： Perry H. Pelley, III
发明人： Perry H. Pelley, III
摘要： A memory (110) having sections of memory cells used ATD to generate the required timing signals, includes ATD generators (189), first summation circuits (180-183), and local summation circuits 185-187. An ATD pulse is generated by the ATD generators (189) when an address signal transitions from one logic state to another. The outputs of the ATD generators (189) are wired-OR connected to input terminals of first summation circuits (180-183). A first summation signal is provided by the first summation circuits (180-183) to each of the local summation circuits (185-187). The local summation circuits (185-187) are positioned in the vicinity of the areas where the timing signals are used. Localized generation of the ATD signals prevents the timing signals for being excessively skewed from each other in different portions of the memory (110).
摘要翻译： 具有使用ATD的存储单元部分生成所需定时信号的存储器（110）包括ATD发生器（189），第一求和电路（180-183）和局部求和电路185-187。 当地址信号从一个逻辑状态转变到另一个逻辑状态时，由ATD发生器（189）产生ATD脉冲。 ATD发生器（189）的输出被或线连接到第一求和电路（180-183）的输入端。 第一求和信号由第一求和电路（180-183）提供给每个局部求和电路（185-187）。 局部求和电路（185-187）位于使用定时信号的区域附近。 ATD信号的本地产生防止定时信号在存储器（110）的不同部分中彼此过度偏斜。
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公开(公告)号：US4928268A
公开(公告)日：1990-05-22
申请号：US342160
申请日：1989-04-21
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/417
CPC分类号： G11C7/1048
摘要： A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.
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