公开(公告)号：US4806799A

公开(公告)日：1989-02-21

申请号：US160885

申请日：1988-02-26

申请人： Perry H. Pelley, III ,  Ruey J. Yu ,  Scott G. Nogle

发明人： Perry H. Pelley, III ,  Ruey J. Yu ,  Scott G. Nogle

IPC分类号： H03K17/567 ,  H03K3/021 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/092 ,  H03K17/10 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/017527 ,  H03K3/021 ,  H03K3/356017

摘要： In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.

摘要翻译： 在包括ECL和CMOS电路的集成电路中，有一个ECL到CMOS转换器，它将ECL逻辑电平转换为CMOS逻辑电平。 为了将ECL转换为CMOS电平，ECL逻辑高电平耦合到提供CMOS逻辑电平的NPN晶体管的基极。 防止ECL逻辑低电平耦合到NPN晶体管的基极。 通过类似的第二电路获得CMOS逻辑高电平，该第二电路响应于其输出耦合到P沟道晶体管的互补ECL信号。 P沟道晶体管提供CMOS逻辑高输出或不导通。

公开(公告)号：US5572467A

公开(公告)日：1996-11-05

申请号：US426995

申请日：1995-04-24

申请人： Hamed Ghassemi ,  Perry H. Pelley, III ,  Scott G. Nogle

发明人： Hamed Ghassemi ,  Perry H. Pelley, III ,  Scott G. Nogle

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1051

摘要： A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

摘要翻译： 同步集成电路存储器（30）在读写操作期间具有从存储器阵列（32）读取的数据与从数据输入寄存器（40）读取的数据之间共享的读出的全局数据线。 比较器/锁存器（50）将新地址与先前地址进行比较，并产生用于选择匹配读出放大器（52）和取消选择常规读出放大器（54）的地址匹配信号。 使用比较器/锁存器（50）对每个列地址信号实现相对快速的地址比较和地址匹配信号生成，并且发射器对每个匹配信号求和以提供地址匹配信号。 使用发射极相加减少了门延迟的数量，从而允许在可以选择常规读出放大器（54）之前产生地址匹配信号，并允许共享读取的全局数据线，而不增加读取全局数据线的访问时间 集成电路存储器（30）。

公开(公告)号：US5140191A

公开(公告)日：1992-08-18

申请号：US610172

申请日：1990-11-05

申请人： Scott G. Nogle ,  Perry H. Pelley, III

发明人： Scott G. Nogle ,  Perry H. Pelley, III

IPC分类号： G11C7/10 ,  H03K19/003

CPC分类号： G11C7/1051 ,  H03K19/00346

摘要： An output buffer for a device such as a memory comprises a voltage regulator, a current source portion, a switching portion, and an output portion. The voltage regulator provides a constant voltage independent of fluctuations between first and second power supply voltages. The current source portion provides first and second currents to first and second nodes to limit the rate at which transistors in the output portion become conductive. The switching portion provides voltage signals on the first and second nodes respectively in response to positive and negative voltage differences between first and second input voltages. The output portion provides an output signal at either a logic high or a logic low voltage respectively in resonse to the voltage signals at the first and second nodes. The current source portion allows the use of faster bipolar transistors to improve the speed of the output buffer while maintaining accepable di/dt.

摘要翻译： 用于诸如存储器的装置的输出缓冲器包括电压调节器，电流源部分，开关部分和输出部分。 电压调节器提供独立于第一和第二电源电压之间的波动的恒定电压。 电流源部分向第一和第二节点提供第一和第二电流以限制输出部分中的晶体管导通的速率。 开关部分响应于第一和第二输入电压之间的正和负电压差分别在第一和第二节点上提供电压信号。 输出部分响应于第一和第二节点处的电压信号，分别以逻辑高电平或逻辑低电压提供输出信号。 电流源部分允许使用更快的双极晶体管来提高输出缓冲器的速度，同时保持可接受的di / dt。

公开(公告)号：US4928268A

公开(公告)日：1990-05-22

申请号：US342160

申请日：1989-04-21

申请人： Scott G. Nogle ,  Perry H. Pelley, III ,  Stephen T. Flannagan ,  Bruce E. Engles

发明人： Scott G. Nogle ,  Perry H. Pelley, III ,  Stephen T. Flannagan ,  Bruce E. Engles

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/1048

摘要： A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.

公开(公告)号：US5303191A

公开(公告)日：1994-04-12

申请号：US824666

申请日：1992-01-23

申请人： John W. Eagan ,  Scott G. Nogle ,  Ruey J. Yu

发明人： John W. Eagan ,  Scott G. Nogle ,  Ruey J. Yu

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  G11C11/417 ,  G11C13/00

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  G11C8/06

摘要： A memory (30) includes input buffers (35, 38, 56), decoders (31, 32, 36), and a memory portion (34). The input buffers (35, 38, 56) include a delay circuit (82) which delays at least one transition of an input signal. The delay circuit (82) includes a compensation circuit (250) which compensates the delay circuit (82) for voltage, temperature, and processing variations. In one embodiment, the delay circuit (82) includes a CMOS inverter (102, 103) with an additional transistor (101) coupled between a source of an inverter transistor (102) and a corresponding power supply voltage. The compensation circuit (250) provides a bias voltage to bias a gate of the transistor (101) to determine the delay of the delay circuit (82). The compensation circuit (250) provides the bias voltage as that voltage which biases the transistor (101) to conduct a precision reference current.

摘要翻译： 存储器（30）包括输入缓冲器（35,38,56），解码器（31,32,36）和存储器部分（34）。 输入缓冲器（35,38,56）包括延迟输入信号的至少一个转换的延迟电路（82）。 延迟电路（82）包括补偿电路（250），该补偿电路补偿延迟电路（82）的电压，温度和处理变化。 在一个实施例中，延迟电路（82）包括具有耦合在反相器晶体管（102）的源极和相应的电源电压之间的附加晶体管（101）的CMOS反相器（102,103）。 补偿电路（250）提供偏置电压以偏置晶体管（101）的栅极以确定延迟电路（82）的延迟。 补偿电路（250）提供偏置电压，作为偏置晶体管（101）以传导精确参考电流的电压。

公开(公告)号：US5623437A

公开(公告)日：1997-04-22

申请号：US532291

申请日：1995-09-22

申请人： Scott G. Nogle ,  Alan S. Roth

发明人： Scott G. Nogle ,  Alan S. Roth

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1051

摘要： A circuit having a combined level conversion and logic function (37, 90, 101, 102, and 103) receives a differential CMOS level input signal, and an input signal having a relatively small logic swing, performs a logic operation, and provides a single-ended CMOS output signal. The circuit (37) includes a CMOS switching portion (71) and a small signal switching portion (75) connected to provide a CMOS output signal that is the result of a logical operation of the input signals. The circuits (37, 90, 101, 102, and 103), eliminate the need for a separate level converter, reducing at least a gate delay, and insuring faster generation of the output signal. Also, the use of the circuit (37) having a combined level conversion and logic function allows the cache TAG (20) to provide read data at the same time that a match signal is generated.

摘要翻译： 具有组合电平转换和逻辑功能（37,90,101,102和103）的电路接收差分CMOS电平输入信号和具有相对小的逻辑摆幅的输入信号，执行逻辑运算，并提供单个 传输的CMOS输出信号。 电路（37）包括CMOS切换部分（71）和小信号切换部分（75），其连接以提供作为输入信号的逻辑运算结果的CMOS输出信号。 电路（37,90,101,102和103）消除了对单独的电平转换器的需要，至少减少门延迟，并确保更快地产生输出信号。 此外，具有组合电平转换和逻辑功能的电路（37）的使用允许高速缓存TAG（20）在产生匹配信号的同时提供读取数据。

公开(公告)号：US5606275A

公开(公告)日：1997-02-25

申请号：US523165

申请日：1995-09-05

申请人： Ali R. Farhang ,  Scott G. Nogle

发明人： Ali R. Farhang ,  Scott G. Nogle

IPC分类号： H03K19/0175 ,  H03H11/28 ,  H03K19/00 ,  H03K19/084

CPC分类号： H03K19/0005

摘要： An output buffer circuit (20) has an output impedance that is adjustable. An external resistor (32) having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit (20). A voltage across the resistor (32) is converted to a digital code using an analog-to-digital (A/D) converter (22). A digital code from the A/D converter (24) is used to adjust a resistance of a binary weighed transistor array (45) to match the resistance of the external resistor (32). A plurality of binary weighted output transistors (153, 154, 155) are selected in response to the digital code to adjust the output impedance to match the characteristic impedance of a load driven by the output buffer circuit (20). The output impedance is easily adjustable by changing the resistance of external resistor (32), allowing the output buffer circuit to drive various load impedances.

摘要翻译： 输出缓冲电路（20）具有可调整的输出阻抗。 具有作为期望输出阻抗的倍数的电阻的外部电阻器（32）耦合到输出缓冲电路（20）。 电阻（32）两端的电压使用模数（A / D）转换器（22）转换成数字码。 来自A / D转换器（24）的数字代码用于调整二进制加权晶体管阵列（45）的电阻以匹配外部电阻器（32）的电阻。 响应于数字代码选择多个二进制加权输出晶体管（153,154,155），以调整输出阻抗以匹配由输出缓冲器电路（20）驱动的负载的特性阻抗。 通过改变外部电阻（32）的电阻可以很容易地调整输出阻抗，允许输出缓冲电路驱动各种负载阻抗。

公开(公告)号：US6011749A

公开(公告)日：2000-01-04

申请号：US49221

申请日：1998-03-27

申请人： Alan S. Roth ,  Scott G. Nogle

发明人： Alan S. Roth ,  Scott G. Nogle

IPC分类号： G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22

摘要： An integrated circuit memory having a plurality of memory cells, output timing control means including frequency measurement means providing a frequency measurement count corresponding to a first frequency of the external clock signal and delay control means generating a delayed clock signal at the first frequency, wherein the delayed clock signal is delayed in time from the external clock signal in proportion to the first frequency, and data output control means outputting data from the plurality of memory cells responsive to the delayed clock signal. A method for adjusting output timing in a memory device including the steps of receiving an external clock signal, measuring a frequency of the external clock signal, generating a frequency count, determining an output delay proportional to the frequency, and generating an output clock at the external frequency and delayed from the external clock signal in proportion to the frequency.

摘要翻译： 一种具有多个存储单元的集成电路存储器，输出定时控制装置包括提供与外部时钟信号的第一频率相对应的频率测量计数的频率测量装置，以及以第一频率产生延迟时钟信号的延迟控制装置， 延迟时钟信号与第一频率成比例地从外部时钟信号延迟，并且数据输出控制装置响应于延迟的时钟信号从多个存储单元输出数据。 一种用于调整存储器件中的输出定时的方法，包括以下步骤：接收外部时钟信号，测量外部时钟信号的频率，产生频率计数，确定与频率成比例的输出延迟，以及在 外部频率和外部时钟信号与频率成比例延迟。

公开(公告)号：US5155703A

公开(公告)日：1992-10-13

申请号：US548809

申请日：1990-07-06

申请人： Scott G. Nogle

发明人： Scott G. Nogle

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/417 ,  G11C11/419

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) bit line load for a memory with improved speed write recovery and improved reliability. Comprises a first bipolar transistor, a resistor, and a second and third bipolar transistors respectively coupled to first and second bit lines of a differential bit line pair. The improvement in speed is accomplished through the use of the bipolar transistors which generally switch faster than corresponding MOS transistors. The first bipolar transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter coupled to the collectors of the second and third bipolar transistors. The resistor is coupled between the collector and emitter of the first bipolar transistor. The bit line load has improved reliability by preventing self-boosting at the bases of the second and third bipolar transistors by decreasing their collector voltages enough during switching to bias them into saturation.

公开(公告)号：US5475635A

公开(公告)日：1995-12-12

申请号：US218450

申请日：1994-03-28

申请人： Scott G. Nogle

发明人： Scott G. Nogle

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C11/419

CPC分类号： G11C7/1048

摘要： A combined global data line load and multiplexer comprises a decoder, a bias generator circuit, at least one output signal line pair, and a plurality of switching portions. The decoder provides a plurality of select signals in response to a portion of an address, each select signal provided at either a logic high voltage or at a logic low voltage. For example, a X4 memory internally organized X8 uses one extra address bit to select between two sets of four global data line pairs to provide as outputs. The bias generator circuit provides a bias signal at a voltage between the logic high and the logic low voltages. The output signal lines are each coupled through a respective resistor to a power supply voltage terminal. Each switching portion provides substantially a differential current between corresponding global data lines to corresponding output signal lines in response to the bias voltage exceeding a voltage of a corresponding select signal.

摘要翻译： 组合的全球数据线负载和多路复用器包括解码器，偏置发生器电路，至少一个输出信号线对和多个开关部分。 解码器响应于地址的一部分提供多个选择信号，每个选择信号以逻辑高电压或逻辑低电压提供。 例如，内部组织的X4内存X8使用一个额外的地址位在两组四个全局数据线对之间进行选择，以提供输出。 偏置发生器电路在逻辑高电平和逻辑低电压之间的电压上提供偏置信号。 输出信号线各自通过相应的电阻器耦合到电源电压端子。 每个开关部分响应于超过相应选择信号的电压的偏置电压，在对应的全局数据线之间基本上提供相应的输出信号线的差分电流。