公开(公告)号：US4806799A

公开(公告)日：1989-02-21

申请号：US160885

申请日：1988-02-26

申请人： Perry H. Pelley, III ,  Ruey J. Yu ,  Scott G. Nogle

发明人： Perry H. Pelley, III ,  Ruey J. Yu ,  Scott G. Nogle

IPC分类号： H03K17/567 ,  H03K3/021 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/092 ,  H03K17/10 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/017527 ,  H03K3/021 ,  H03K3/356017

摘要： In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.

摘要翻译： 在包括ECL和CMOS电路的集成电路中，有一个ECL到CMOS转换器，它将ECL逻辑电平转换为CMOS逻辑电平。 为了将ECL转换为CMOS电平，ECL逻辑高电平耦合到提供CMOS逻辑电平的NPN晶体管的基极。 防止ECL逻辑低电平耦合到NPN晶体管的基极。 通过类似的第二电路获得CMOS逻辑高电平，该第二电路响应于其输出耦合到P沟道晶体管的互补ECL信号。 P沟道晶体管提供CMOS逻辑高输出或不导通。

公开(公告)号：US4928268A

公开(公告)日：1990-05-22

申请号：US342160

申请日：1989-04-21

申请人： Scott G. Nogle ,  Perry H. Pelley, III ,  Stephen T. Flannagan ,  Bruce E. Engles

发明人： Scott G. Nogle ,  Perry H. Pelley, III ,  Stephen T. Flannagan ,  Bruce E. Engles

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/1048

摘要： A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.

公开(公告)号：US5572467A

公开(公告)日：1996-11-05

申请号：US426995

申请日：1995-04-24

申请人： Hamed Ghassemi ,  Perry H. Pelley, III ,  Scott G. Nogle

发明人： Hamed Ghassemi ,  Perry H. Pelley, III ,  Scott G. Nogle

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1051

摘要： A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

摘要翻译： 同步集成电路存储器（30）在读写操作期间具有从存储器阵列（32）读取的数据与从数据输入寄存器（40）读取的数据之间共享的读出的全局数据线。 比较器/锁存器（50）将新地址与先前地址进行比较，并产生用于选择匹配读出放大器（52）和取消选择常规读出放大器（54）的地址匹配信号。 使用比较器/锁存器（50）对每个列地址信号实现相对快速的地址比较和地址匹配信号生成，并且发射器对每个匹配信号求和以提供地址匹配信号。 使用发射极相加减少了门延迟的数量，从而允许在可以选择常规读出放大器（54）之前产生地址匹配信号，并允许共享读取的全局数据线，而不增加读取全局数据线的访问时间 集成电路存储器（30）。

公开(公告)号：US5140191A

公开(公告)日：1992-08-18

申请号：US610172

申请日：1990-11-05

申请人： Scott G. Nogle ,  Perry H. Pelley, III

发明人： Scott G. Nogle ,  Perry H. Pelley, III

IPC分类号： G11C7/10 ,  H03K19/003

CPC分类号： G11C7/1051 ,  H03K19/00346

摘要： An output buffer for a device such as a memory comprises a voltage regulator, a current source portion, a switching portion, and an output portion. The voltage regulator provides a constant voltage independent of fluctuations between first and second power supply voltages. The current source portion provides first and second currents to first and second nodes to limit the rate at which transistors in the output portion become conductive. The switching portion provides voltage signals on the first and second nodes respectively in response to positive and negative voltage differences between first and second input voltages. The output portion provides an output signal at either a logic high or a logic low voltage respectively in resonse to the voltage signals at the first and second nodes. The current source portion allows the use of faster bipolar transistors to improve the speed of the output buffer while maintaining accepable di/dt.

摘要翻译： 用于诸如存储器的装置的输出缓冲器包括电压调节器，电流源部分，开关部分和输出部分。 电压调节器提供独立于第一和第二电源电压之间的波动的恒定电压。 电流源部分向第一和第二节点提供第一和第二电流以限制输出部分中的晶体管导通的速率。 开关部分响应于第一和第二输入电压之间的正和负电压差分别在第一和第二节点上提供电压信号。 输出部分响应于第一和第二节点处的电压信号，分别以逻辑高电平或逻辑低电压提供输出信号。 电流源部分允许使用更快的双极晶体管来提高输出缓冲器的速度，同时保持可接受的di / dt。

公开(公告)号：US4943743A

公开(公告)日：1990-07-24

申请号：US172515

申请日：1988-03-24

申请人： Perry H. Pelley, III ,  Ruey J. Yu

发明人： Perry H. Pelley, III ,  Ruey J. Yu

IPC分类号： H03K19/0175

CPC分类号： H03K19/017527

摘要： An input buffer for translating TTL level signals to ECL level signals has a level shifter having a first and a second inupt transistor. The first input transistor receives the input signal and the second transistor receives a reference voltage. First and second transistor loads are coupled to the first and second transistors, respectively. Both the first and second loads are biased to the same saturation current. The saturation current is derived from a current source. The reference voltage is set at a voltage which is between the maximum voltage of a logic low of the input signal and the minimum voltage of a high of the input signal. The deferential level shifter develops a voltage differential which is converted to ECL level signals by a differential amplifier.

摘要翻译： 用于将TTL电平信号转换为ECL电平信号的输入缓冲器具有具有第一和第二中断晶体管的电平移位器。 第一输入晶体管接收输入信号，第二晶体管接收参考电压。 第一和第二晶体管负载分别耦合到第一和第二晶体管。 第一和第二负载都被偏置到相同的饱和电流。 饱和电流源自电流源。 参考电压设定在输入信号的逻辑低电平的最大电压与输入信号的最高电压之间的电压。 推导电平转换器产生一个差分放大器转换成ECL电平信号的电压差。

公开(公告)号：US08294483B2

公开(公告)日：2012-10-23

申请号：US12130173

申请日：2008-05-30

申请人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

发明人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3025

摘要： A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

摘要翻译： 测试系统包括测试仪探头和多个集成电路。 使用无载波超宽带（UWB）射频（RF）将测试广播到多个集成电路。 所有多个集成电路同时接收通过无载波UWB RF测试输入信号，并且所有多个集成电路都运行测试并基于测试输入信号提供结果。 因此，同时测试多个集成电路，这大大减少了测试时间。 此外，与集成电路的物理接触也不会妨碍测试。

公开(公告)号：US07440354B2

公开(公告)日：2008-10-21

申请号：US11433998

申请日：2006-05-15

申请人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

发明人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/144 ,  G11C8/10

摘要： A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

摘要翻译： 存储器包括包括多个字线的位单元阵列和具有提供预解码值的输出的地址解码电路。 地址解码电路包括具有第一栅极氧化物厚度的第一多个晶体管。 存储器还包括字线驱动器电路，其具有耦合到地址解码电路的输出的输入和多个输出，每个输出耦合到多个字线中的相应字线。 字线驱动器包括具有大于第一栅极氧化物厚度的第二栅极氧化物厚度的第二多个晶体管。 还提供了一种操作存储器的方法。

公开(公告)号：US4551641A

公开(公告)日：1985-11-05

申请号：US554517

申请日：1983-11-23

申请人： Perry H. Pelley, III

发明人： Perry H. Pelley, III

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/4091 ,  H03K5/24

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second differential amplifier coupled to the pair of bit lines which is enabled a predetermined time duration following the occurrence of the first signal.

摘要翻译： 读出放大器耦合到一对位线，用于检测和放大它们之间的电压差。 读出放大器具有耦合到响应于第一信号使能的一对位线对的第一差分放大器。 读出放大器还具有耦合到一对位线的第二差分放大器，其在第一信号的出现之后被允许预定的持续时间。

公开(公告)号：US08090913B2

公开(公告)日：2012-01-03

申请号：US12972878

申请日：2010-12-20

申请人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. Pessoa

发明人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. Pessoa

IPC分类号： G06F12/08

CPC分类号： G06F15/16

摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

摘要翻译： 系统在第一相干组中具有第一多个核心。 每个核心以数据包传输数据。 核心直接串联耦合以形成串行路径。 数据包沿串行路径传输。 串行路径在一端耦合到分组交换机。 分组交换机耦合到存储器。 第一多个核心和分组交换机在集成电路上。 存储器可能集成在或不在集成电路上。 在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。 可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

公开(公告)号：US07941637B2

公开(公告)日：2011-05-10

申请号：US12103250

申请日：2008-04-15

申请人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. C. Pessoa

发明人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. C. Pessoa

IPC分类号： G06F15/80

CPC分类号： G06F15/16

摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

摘要翻译： 系统在第一相干组中具有第一多个核心。 每个核心以数据包传输数据。 核心直接串联耦合以形成串行路径。 数据包沿串行路径传输。 串行路径在一端耦合到分组交换机。 分组交换机耦合到存储器。 第一多个核心和分组交换机在集成电路上。 存储器可能集成在或不在集成电路上。 在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。 可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。