公开(公告)号：US20250157508A1

公开(公告)日：2025-05-15

申请号：US18641578

申请日：2024-04-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/16

Abstract: The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

公开(公告)号：US20240028211A1

公开(公告)日：2024-01-25

申请号：US18161900

申请日：2023-01-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Teng-Hao Yeh ,  Chih-Chang Hsieh ,  Chun-Hsiung Hung ,  Yung-Chun LI

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/28

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

公开(公告)号：US20230238037A1

公开(公告)日：2023-07-27

申请号：US17583254

申请日：2022-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Yu-Hsuan LIN ,  Feng-Min LEE ,  Yung-Chun LI

IPC: G11C7/06 ,  G11C7/14 ,  G11C15/04 ,  G11C16/34 ,  G06V40/16

CPC classification number: G11C7/067 ,  G11C7/14 ,  G11C15/04 ,  G11C16/34 ,  G06V40/172

Abstract: The application provides a content addressable memory (CAM) memory device and a method for searching and comparing data thereof. The CAM memory device comprises: a plurality of CAM memory strings; and a sensing amplifier circuit coupled to the CAM memory strings; wherein in data searching, a search data is compared with a storage data stored in the CAM memory strings, the CAM memory strings generate a plurality of memory string currents, the sensing amplifier circuit senses the memory string currents to generate a plurality of sensing results: based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

公开(公告)号：US20230027384A1

公开(公告)日：2023-01-26

申请号：US17511802

申请日：2021-10-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Yung-Chun LI

IPC: G11C11/56 ,  G11C16/10

Abstract: A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2∧N-1 or 2∧N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2∧N-1 or 2∧N verify levels.

公开(公告)号：US20210375357A1

公开(公告)日：2021-12-02

申请号：US17035885

申请日：2020-09-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Wei-Chen WANG

IPC: G11C11/56 ,  G11C16/10 ,  G06F12/02

Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

公开(公告)号：US20200051620A1

公开(公告)日：2020-02-13

申请号：US16057871

申请日：2018-08-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Ping-Hsien LIN

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34

Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.