公开(公告)号：US20220334964A1

公开(公告)日：2022-10-20

申请号：US17542557

申请日：2021-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F12/0802

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

公开(公告)号：US20250157548A1

公开(公告)日：2025-05-15

申请号：US18610368

申请日：2024-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  Shang-Ting LIN

IPC: G11C16/26 ,  G11C16/04

Abstract: The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.

公开(公告)号：US20230410856A1

公开(公告)日：2023-12-21

申请号：US17845008

申请日：2022-06-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Yu-Ming HUANG

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/1096

Abstract: A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.

公开(公告)号：US20220334757A1

公开(公告)日：2022-10-20

申请号：US17403927

申请日：2021-08-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Han-Wen HU ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F3/06

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

公开(公告)号：US20210081274A1

公开(公告)日：2021-03-18

申请号：US16571260

申请日：2019-09-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Ping-Hsien LIN ,  Kun-Chi CHIANG ,  Chien-Chung HO

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C11/409 ,  G11C11/4074

Abstract: A memory data management method includes the following steps: reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to enhance a first state data of the data for exceeding a first threshold, to enhance a second state data of the data for exceeding a second threshold, and to enhance a third state data of the data for exceeding a third threshold.

公开(公告)号：US20250158628A1

公开(公告)日：2025-05-15

申请号：US18736681

申请日：2024-06-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  BO-RONG LIN ,  Huai-Mu WANG ,  Chih-Huai SHIH

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/50

Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.

公开(公告)号：US20250156420A1

公开(公告)日：2025-05-15

申请号：US18655472

申请日：2024-05-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Huai SHIH ,  Han-Wen HU ,  Huai-Mu WANG ,  Yung-Chun LI

IPC: G06F16/2455 ,  G06F16/28

Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.

公开(公告)号：US20240386958A1

公开(公告)日：2024-11-21

申请号：US18785113

申请日：2024-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Yu-Hsuan LIN ,  Feng-Min LEE ,  Yung-Chun LI

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/26

Abstract: The application provides a content addressable memory (CAM) device and a method for searching and comparing data thereof. The CAM device comprises: a plurality of memory strings; and a sensing amplifier circuit coupled to the memory strings; wherein in data searching, a search data is compared with a storage data stored in the memory strings, the memory strings generate a plurality of string currents, the sensing amplifier circuit senses the string currents to generate a plurality of sensing results; based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

公开(公告)号：US20230221956A1

公开(公告)日：2023-07-13

申请号：US17830453

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F9/30 ,  G06F7/544 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/3001 ,  G06F7/5443 ,  G11C16/3404 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20230221882A1

公开(公告)日：2023-07-13

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.