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公开(公告)号：US20170117849A1
公开(公告)日：2017-04-27
申请号：US15239818
申请日：2016-08-17
Applicant: MEDIATEK INC.
Inventor： Chao-Ching Hung , Po-Chun Huang , Yu-Li Hsueh
CPC classification number: H03B5/1234 , H03B1/00 , H03B5/06 , H03B5/10 , H03B5/1212 , H03B5/1215 , H03B2200/0094 , H03L5/00 , H03L7/099
Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.
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公开(公告)号：US20240030872A1
公开(公告)日：2024-01-25
申请号：US18113623
申请日：2023-02-24
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Chen , Chao-Ching Hung , Yu-Li Hsueh
CPC classification number: H03B5/366 , H03B5/04 , H03B5/1265 , H03B2200/0094
Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.
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公开(公告)号：US11677433B2
公开(公告)日：2023-06-13
申请号：US16152391
申请日：2018-10-04
Applicant: MEDIATEK INC.
Inventor： Jui-Lin Hsu , Chao-Ching Hung , Tzu-Chin Lin , Wei-Hsiu Hsu , Yu-Li Hsueh , Jing-Hong Conan Zhan , Chih-Ming Hung
CPC classification number: H04B1/403 , G01S7/03 , G01S7/032 , H03B5/12 , H03K5/135 , H04B7/2662 , H03B2200/008
Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.
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公开(公告)号：US10374588B2
公开(公告)日：2019-08-06
申请号：US15717919
申请日：2017-09-27
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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公开(公告)号：US09853648B2
公开(公告)日：2017-12-26
申请号：US14737619
申请日：2015-06-12
Applicant: MEDIATEK Inc.
Inventor： Richard Y. Su , Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Yi-Chien Tsai
Abstract: A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.
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Patent Agency Ranking
公开(公告)号：US12113480B2
公开(公告)日：2024-10-08
申请号：US18113623
申请日：2023-02-24
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Chen , Chao-Ching Hung , Yu-Li Hsueh
CPC classification number: H03B5/366 , H03B5/04 , H03B5/1265 , H03B2200/0094
Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.
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17.发明公开公开(公告)号：US20240171161A1
公开(公告)日：2024-05-23
申请号：US18223537
申请日：2023-07-18
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Chen , Kairen Fong , Chao-Ching Hung , Yu-Li Hsueh
CPC classification number: H03K5/01 , G04F10/005 , H03K3/037
Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.
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公开(公告)号：US20220113374A1
公开(公告)日：2022-04-14
申请号：US17558502
申请日：2021-12-21
Applicant: MEDIATEK INC.
Inventor： Tzu-Chin Lin , Chih-Ming Hung , Jui-Lin Hsu , Chao-Ching Hung , Bao-Chi Peng
Abstract: A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.
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公开(公告)号：US11237249B2
公开(公告)日：2022-02-01
申请号：US16168853
申请日：2018-10-24
Applicant: MEDIATEK INC.
Inventor： Tzu-Chin Lin , Chih-Ming Hung , Jui-Lin Hsu , Chao-Ching Hung , Bao-Chi Peng
Abstract: A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.
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公开(公告)号：US11139818B1
公开(公告)日：2021-10-05
申请号：US17124518
申请日：2020-12-17
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Yu-Li Hsueh , Chao-Ching Hung
Abstract: A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.
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