公开(公告)号：US11606063B2

公开(公告)日：2023-03-14

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US20220209715A1

公开(公告)日：2022-06-30

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US11309835B2

公开(公告)日：2022-04-19

申请号：US17306960

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

公开(公告)号：US09906209B2

公开(公告)日：2018-02-27

申请号：US15498525

申请日：2017-04-27

Applicant: MEDIATEK Inc.

Inventor： Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03K19/003 ,  H04B1/00 ,  H03L7/00 ,  H03H11/30 ,  H03K5/159 ,  H03K19/0175 ,  H03K19/00 ,  H04B1/04 ,  H04B1/16 ,  H04L25/02 ,  H03L1/02 ,  H03L7/18 ,  H03L7/10 ,  H03L7/113 ,  H03K19/21

CPC classification number: H03H11/30 ,  H03K5/159 ,  H03K19/0005 ,  H03K19/017545 ,  H03K19/21 ,  H03L1/00 ,  H03L1/022 ,  H03L7/0816 ,  H03L7/103 ,  H03L7/113 ,  H03L7/18 ,  H04B1/0475 ,  H04B1/1638 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

Abstract: A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.