公开(公告)号：US20230260866A1

公开(公告)日：2023-08-17

申请号：US18157159

申请日：2023-01-20

Applicant: MEDIATEK INC.

Inventor： Yin-Fa CHEN ,  Bo-Jiun YANG ,  Ta-Jen YU ,  Bo-Hao MA ,  Chih-Wei CHANG ,  Tsung-Yu PAN ,  Tai-Yu CHEN ,  Shih-Chin LIN ,  Wen-Sung HSU

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L23/13

CPC classification number: H01L23/3675 ,  H01L24/73 ,  H01L24/16 ,  H01L24/32 ,  H01L24/17 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/13 ,  H01L2924/1511 ,  H01L2924/15151 ,  H01L2924/152 ,  H01L2924/15331 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/17051 ,  H01L2924/1011

Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.

公开(公告)号：US20230153958A1

公开(公告)日：2023-05-18

申请号：US18151104

申请日：2023-01-06

Applicant: MEDIATEK INC.

Inventor： Jen Cheng LUNG ,  Pei-Kuei TSUNG ,  Chih-Wei CHEN ,  Yao-Sheng WANG ,  Shih-Che CHEN ,  Yu-Sheng LIN ,  Chih-Wen GOO ,  Shih-Chin LIN ,  Huang TSUNG-SHIAN ,  Ying-Chieh CHEN

IPC: G06T5/00 ,  G06T5/50 ,  G06T3/00 ,  G06T7/254 ,  G06T3/40

CPC classification number: G06T5/002 ,  G06T5/50 ,  G06T3/0093 ,  G06T7/254 ,  G06T3/4053 ,  G06T2207/20084 ,  G06T2207/20224

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

公开(公告)号：US20210174473A1

公开(公告)日：2021-06-10

申请号：US17113397

申请日：2020-12-07

Applicant: MEDIATEK INC.

Inventor： Jen Cheng LUNG ,  Pei-Kuei TSUNG ,  Chih-Wei CHEN ,  Yao-Sheng WANG ,  Shih-Che CHEN ,  Yu-Sheng LIN ,  Chih-Wen GOO ,  Shih-Chin LIN ,  Huang TSUNG-SHIAN ,  Ying-Chieh CHEN

IPC: G06T5/00 ,  G06T5/50 ,  G06T3/00 ,  G06T3/40 ,  G06T7/254

Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

公开(公告)号：US20130313698A1

公开(公告)日：2013-11-28

申请号：US13896616

申请日：2013-05-17

Applicant: MediaTek Inc.

Inventor： Tai-Yu CHEN ,  Chung-Fa LEE ,  Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/36

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球。