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    Hash function with perfect hash component
    12.
    发明授权
    Hash function with perfect hash component 有权

    公开(公告)号：US12130745B2

    公开(公告)日：2024-10-29

    申请号：US18073586

    申请日：2022-12-02

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Avi Urman

    IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/0893 ,  H04L9/06

    CPC classification number: G06F12/0893 ,  G06F12/0802 ,  H04L9/0643

    Abstract: A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max

    Analysis of events in an integrated circuit using cause tree and buffer
    13.
    发明授权
    Analysis of events in an integrated circuit using cause tree and buffer 有权

    公开(公告)号：US11966310B1

    公开(公告)日：2024-04-23

    申请号：US17981508

    申请日：2022-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

    Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

    SYNCHRONIZED RATE CONTROL AT RATE LIMITER
    14.
    发明公开
    SYNCHRONIZED RATE CONTROL AT RATE LIMITER 审中-公开

    公开(公告)号：US20230361900A1

    公开(公告)日：2023-11-09

    申请号：US18107442

    申请日：2023-02-08

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Liron Mula ,  Natan Manevich

    IPC: H04J3/06 ,  H04L47/25

    CPC classification number: H04J3/0652 ,  H04L47/25 ,  H04J3/0667

    Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.

    Template-based packet parsing
    15.
    发明授权
    Template-based packet parsing 有权

    公开(公告)号：US11711453B2

    公开(公告)日：2023-07-25

    申请号：US17508998

    申请日：2021-10-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

    IPC: G06F15/173 ,  H04L69/22 ,  H04L69/324 ,  H04L69/323

    CPC classification number: H04L69/22 ,  H04L69/323 ,  H04L69/324

    Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

    Packet switches
    16.
    发明授权
    Packet switches 有权

    公开(公告)号：US11711318B1

    公开(公告)日：2023-07-25

    申请号：US17648260

    申请日：2022-01-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ioannis (Giannis) Patronas ,  Michael Gandelman ,  Liron Mula ,  Aviad Levy ,  Lion Levi ,  Jose Yallouz ,  Paraskevas Bakopoulos ,  Elad Mentovich

    IPC: H04L49/00 ,  H04L49/101

    CPC classification number: H04L49/3027 ,  H04L49/101 ,  H04L49/3018

    Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

    Head-of-queue blocking for multiple lossless queues
    18.
    发明申请
    Head-of-queue blocking for multiple lossless queues 有权

    公开(公告)号：US20220417161A1

    公开(公告)日：2022-12-29

    申请号：US17902936

    申请日：2022-09-05

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Lion Levi ,  Yuval Shpigelman

    IPC: H04L47/26 ,  H04L47/2425 ,  H04L47/30 ,  H04L47/62 ,  H04L47/10

    Abstract: A network element includes a transmit-queue for transmitting packets from at least two sources, each source having a predefined priority level, to a headroom buffer in a peer network element. Flow-control circuitry receives from the peer network element signaling that indicates a number of credits for transmitting packets to the peer network element, manages a current number of credits available for transmission from the transmit-queue, responsive to the signaling, selects a threshold priority based on the current number of credits for the transmit-queue; and transmits packets associated with data sources of the transmit-queue that are higher in priority than the threshold priority, and refrain from transmitting other packets associated with the transmit-queue.

    Hardware Clock with Built-In Accuracy Check
    20.
    发明申请
    Hardware Clock with Built-In Accuracy Check 有权

    公开(公告)号：US20220224500A1

    公开(公告)日：2022-07-14

    申请号：US17148605

    申请日：2021-01-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

    IPC: H04L7/00

    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

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