公开(公告)号：US11575594B2

公开(公告)日：2023-02-07

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: G06F15/16 ,  H04L45/00 ,  H04L41/12 ,  H04L45/48 ,  H04L12/44

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

公开(公告)号：US20220263776A1

公开(公告)日：2022-08-18

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L12/823

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US20220131826A1

公开(公告)日：2022-04-28

申请号：US17079543

申请日：2020-10-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Vladimir Koushnir ,  Matty Kadosh ,  Gil Bloch ,  Aviad Levy ,  Liran Liss ,  Dvir Libhaber

IPC: H04L29/12 ,  H04L12/751

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

公开(公告)号：US20210218808A1

公开(公告)日：2021-07-15

申请号：US17147487

申请日：2021-01-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Richard Graham ,  Lion Levi ,  Daniel Marcovitch ,  Larry R. Dennison ,  Aviad Levy ,  Noam Bloch ,  Gil Bloch

IPC: H04L29/08

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

公开(公告)号：US10218642B2

公开(公告)日：2019-02-26

申请号：US15469643

申请日：2017-03-27

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Liron Mula ,  Sagi Kuks ,  George Elias ,  Eyal Srebro ,  Ofir Merdler ,  Amiad Marelli ,  Lion Levi ,  Oded Zemer ,  Yoav Benros

IPC: H04L12/935 ,  H04L12/933 ,  H04L12/937 ,  H04L12/931 ,  H04L12/861

Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.

公开(公告)号：US11750699B2

公开(公告)日：2023-09-05

申请号：US17147487

申请日：2021-01-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Richard Graham ,  Lion Levi ,  Daniel Marcovitch ,  Larry R. Dennison ,  Aviad Levy ,  Noam Bloch ,  Gil Bloch

IPC: H04L67/1097 ,  H04L67/60

CPC classification number: H04L67/1097 ,  H04L67/60

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

公开(公告)号：US11558316B2

公开(公告)日：2023-01-17

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L49/90 ,  H04L47/32 ,  H04L49/9047

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US11552882B2

公开(公告)日：2023-01-10

申请号：US17211904

申请日：2021-03-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Gil Mey-Tal ,  Daniel Klein

IPC: H04L12/703 ,  H04L12/721 ,  H04L12/707 ,  H04L12/717 ,  H04L45/28 ,  H04L45/42 ,  H04L45/00 ,  H04L45/12

Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.

公开(公告)号：US20220311702A1

公开(公告)日：2022-09-29

申请号：US17211904

申请日：2021-03-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Gil Mey-Tal ,  Daniel Klein

IPC: H04L12/703 ,  H04L12/721 ,  H04L12/707 ,  H04L12/717

Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.

公开(公告)号：US11425027B2

公开(公告)日：2022-08-23

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L45/00 ,  H04L45/02 ,  H04L45/122 ,  H04L49/00

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.