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    Fail-Safe Clock Monitor with Fault Injection
    11.
    发明申请
    Fail-Safe Clock Monitor with Fault Injection 审中-公开

    公开(公告)号：US20200012313A1

    公开(公告)日：2020-01-09

    申请号：US16143841

    申请日：2018-09-27

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Aditya Nukala

    IPC: G06F1/14 ,  G06F1/08 ,  G06F11/16 ,  G06F1/10

    Abstract: A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

    Digital period divider
    14.
    发明授权
    Digital period divider 有权
    数字周期分频器

    公开(公告)号：US08908823B2

    公开(公告)日：2014-12-09

    申请号：US14200317

    申请日：2014-03-07

    Applicant: Microchip Technology Incorporated

    Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

    IPC: G01P3/00 ,  H03K23/00

    CPC classification number: H03K23/00 ,  G01P3/481 ,  G01P3/486 ,  G01P3/487 ,  G01P3/488 ,  G01P3/489 ,  H02P6/17 ,  H03K21/38 ,  H03K23/40

    Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

    Abstract translation: 数字周期分配器具有具有R个最低有效位（LSB）和P个最高有效位（MSB）的第一计数器，其具有计数输入和复位输入，其中所述计数输入接收第一时钟信号，并且所述复位输入接收第二时钟 信号; 具有P位并与第一计数器的P位耦合的锁存器; 具有P位和计数输入和复位输入的第二计数器，其中所述计数输入接收所述第一时钟信号; 以及第一比较器，用于将锁存器的P位与第二计数器的P位进行比较并产生输出信号，其中输出信号也被馈送到第二计数器的复位输入。

    Method For Enlarging Data Memory In An Existing Microprocessor Architecture With Limited Memory Addressing
    16.
    发明申请
    Method For Enlarging Data Memory In An Existing Microprocessor Architecture With Limited Memory Addressing 有权
    在现有的微处理器体系结构中扩展数据存储器的方法有限的存储器寻址

    公开(公告)号：US20170017431A1

    公开(公告)日：2017-01-19

    申请号：US15209543

    申请日：2016-07-13

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Joseph Julicher ,  Jacobus Albertus Van Eeden

    IPC: G06F3/06 ,  G06F9/30

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/342 ,  G06F9/35

    Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

    Abstract translation: 一种用于扩展用于微处理器架构的数据存储器的方法，其使用存储体选择访问方案来访问被划分为多个存储体的数据存储器。 存储区选择寄存器被配置为选择存储体，并且微处理器架构具有指令集，其具有用于选择存储体的专用指令。 专用存储体选择指令的操作码最多提供n个位有效载荷，从而提供配置为选择最多2n个存储体的地址值。 该方法具有以下步骤：使用为新的存储体选择指令提供有效载荷的m位的测试指令的操作码，其中m> n; 并使用专用存储体选择指令的操作码进行新的测试指令。

    Processor device with instruction trace capabilities
    17.
    发明授权
    Processor device with instruction trace capabilities 有权
    具有指令跟踪功能的处理器设备

    公开(公告)号：US09377507B2

    公开(公告)日：2016-06-28

    申请号：US13888357

    申请日：2013-05-06

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G06F11/00 ,  G01R31/3177 ,  G06F11/36

    CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

    DIGITAL PERIOD DIVIDER
    18.
    发明申请
    DIGITAL PERIOD DIVIDER 审中-公开
    数字分时器

    公开(公告)号：US20150219474A1

    公开(公告)日：2015-08-06

    申请号：US14608753

    申请日：2015-01-29

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

    IPC: G01D5/14 ,  G01D5/26

    CPC classification number: G01D5/142 ,  G01D5/2451 ,  G01D5/26 ,  G01P3/481 ,  G01P3/486 ,  G01P3/488 ,  G01P3/489 ,  H02P6/16 ,  H02P23/22 ,  H03K21/38

    Abstract: A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeeding pulses of the input output signal. In an enhancement, the system may also have a missing pulse detector which is operable to compare a current interval with a parameter to determine whether a pulse is missing in the input signal.

    Abstract translation: 系统可以具有产生与由旋转输入信号限定的角度成比例的输出信号的数字周期分配器和间隔测量单元，其确定由输入输出信号的后续脉冲定义的间隔的间隔时间。 在增强中，系统还可以具有丢失的脉冲检测器，其可操作以将当前间隔与参数进行比较，以确定输入信号中脉冲是否丢失。

    Device Having Configurable Breakpoint Based on Interrupt Status
    19.
    发明申请
    Device Having Configurable Breakpoint Based on Interrupt Status 有权
    具有基于中断状态的可配置断点的器件

    公开(公告)号：US20130297975A1

    公开(公告)日：2013-11-07

    申请号：US13888370

    申请日：2013-05-07

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G06F11/36

    CPC classification number: G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。

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