公开(公告)号：US11508444B2

公开(公告)日：2022-11-22

申请号：US17199524

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/30

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US11488677B2

公开(公告)日：2022-11-01

申请号：US17247435

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US20220276806A1

公开(公告)日：2022-09-01

申请号：US17742294

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy C. Kavalipurapu ,  Chang H. Siau ,  Shigekazu Yamada

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.

公开(公告)号：US20240393952A1

公开(公告)日：2024-11-28

申请号：US18790552

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Chang H. Siau ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: A memory device including a first plane group, a second plane group and a multiplexer circuit. The multiplexer circuit is coupled to a first input/output (I/O) interface and a second I/O interface. The multiplexer circuit enables the first I/O interface to access the first plane group and the second plane group and enables the second I/O interface to access the first plane group and the second plane group.

公开(公告)号：US11791003B2

公开(公告)日：2023-10-17

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US20230046283A1

公开(公告)日：2023-02-16

申请号：US17980871

申请日：2022-11-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US20220208283A1

公开(公告)日：2022-06-30

申请号：US17199524

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US20220068325A1

公开(公告)日：2022-03-03

申请号：US17034540

申请日：2020-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Michele Piccardi ,  Qui V. Nguyen

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

公开(公告)号：US20220066894A1

公开(公告)日：2022-03-03

申请号：US17396083

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Lu Tong ,  Kristopher Kopel ,  Sheng-Huang Lee ,  Chang H. Siau

IPC: G06F11/20 ,  G11C16/04

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

公开(公告)号：US12136607B2

公开(公告)日：2024-11-05

申请号：US17718217

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H10B41/41

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.