公开(公告)号：US20250029957A1

公开(公告)日：2025-01-23

申请号：US18906093

申请日：2024-10-03

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Raj K. Bansal ,  Takehiro Hasegawa ,  Chang H. Siau

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H10B41/41

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

公开(公告)号：US11861236B2

公开(公告)日：2024-01-02

申请号：US17742294

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy C. Kavalipurapu ,  Chang H. Siau ,  Shigekazu Yamada

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.

公开(公告)号：US11437318B2

公开(公告)日：2022-09-06

申请号：US16900204

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US12079479B2

公开(公告)日：2024-09-03

申请号：US17672026

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Chang H. Siau ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

公开(公告)号：US11875861B2

公开(公告)日：2024-01-16

申请号：US17980871

申请日：2022-11-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/0425 ,  G11C16/26 ,  G11C16/30

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US20230068580A1

公开(公告)日：2023-03-02

申请号：US17672026

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Chang H. Siau ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

公开(公告)号：US20210391257A1

公开(公告)日：2021-12-16

申请号：US16900204

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/535

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US11670346B2

公开(公告)日：2023-06-06

申请号：US17034540

申请日：2020-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Michele Piccardi ,  Qui V. Nguyen

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/22 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C7/1018 ,  G11C7/1096 ,  G11C7/222 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

公开(公告)号：US20220415794A1

公开(公告)日：2022-12-29

申请号：US17929638

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Qui V. Nguyen ,  Chang H. Siau

IPC: H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11582 ,  H01L23/535

Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

公开(公告)号：US11537484B2

公开(公告)日：2022-12-27

申请号：US17396083

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Lu Tong ,  Kristopher Kopel ,  Sheng-Huang Lee ,  Chang H. Siau

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/26

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).