公开(公告)号：US20180342298A1

公开(公告)日：2018-11-29

申请号：US16036549

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  H01L49/02 ,  H01L27/115 ,  H01L27/105 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09966451B1

公开(公告)日：2018-05-08

申请号：US15686101

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Changhyun Lee

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L29/512 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the conductive levels. The conductive levels have projections above and below the recesses. The projections have outer edges. An outer periphery of an individual conductive level is defined by a straight-line boundary extending from the outer edge of the projection above the recess in the individual conductive level to the outer edge of the projection below the recess in the individual conductive level. A depth of the recess is defined as a horizontal distance from the straight-line boundary to an innermost periphery of the recess. The recesses have depths of at least about 5 nm. Charge-blocking regions extend within the recesses. Charge-storage structures are along the charge-blocking regions. Gate dielectric material is along the charge-storage structures. Channel material is along the gate dielectric material.

公开(公告)号：US20170352681A1

公开(公告)日：2017-12-07

申请号：US15659482

申请日：2017-07-25

Applicant: Micron Technology, Inc.

Inventor： Changhyun Lee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11556 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.

公开(公告)号：US09773882B1

公开(公告)日：2017-09-26

申请号：US15405141

申请日：2017-01-12

Applicant: Micron Technology, Inc.

Inventor： Changhyun Lee

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/512 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the conductive levels. The conductive levels have projections above and below the recesses. The projections have outer edges. An outer periphery of an individual conductive level is defined by a straight-line boundary extending from the outer edge of the projection above the recess in the individual conductive level to the outer edge of the projection below the recess in the individual conductive level. A depth of the recess is defined as a horizontal distance from the straight-line boundary to an innermost periphery of the recess. The recesses have depths of at least about 5 nm. Charge-blocking regions extend within the recesses. Charge-storage structures are along the charge-blocking regions. Gate dielectric material is along the charge-storage structures. Channel material is along the gate dielectric material.

公开(公告)号：US11335404B2

公开(公告)日：2022-05-17

申请号：US17080553

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10360979B2

公开(公告)日：2019-07-23

申请号：US16036549

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105 ,  H01L27/115 ,  H01L49/02

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10026480B2

公开(公告)日：2018-07-17

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C11/56 ,  H01L27/105 ,  G11C16/34

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09905575B2

公开(公告)日：2018-02-27

申请号：US15659482

申请日：2017-07-25

Applicant: Micron Technology, Inc.

Inventor： Changhyun Lee

IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11556 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.