公开(公告)号：US11239117B1

公开(公告)日：2022-02-01

申请号：US17004084

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Scott E. Sills

IPC: H01L21/8234 ,  H01L21/822 ,  H01L29/66 ,  H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L21/02 ,  H01L27/06

Abstract: Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.

公开(公告)号：US11227864B1

公开(公告)日：2022-01-18

申请号：US16986610

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Scott E. Sills

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: Systems, methods and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes forming elongated vertical, pillar columns with sidewalls in a vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical openings. Portions of the first conductive material are removed to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns. A second vertical opening is formed through the vertical stack to expose a first region of the sacrificial material. A third vertical opening is formed through the vertical stack to in which to form a storage node electrically coupled to the first source/drain material.

公开(公告)号：US20210313445A1

公开(公告)日：2021-10-07

申请号：US17348718

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L45/00 ,  H01L29/08 ,  H01L29/872 ,  H01L21/28 ,  H01L21/283 ,  H01L29/88

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US11101218B2

公开(公告)日：2021-08-24

申请号：US16112333

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Sumeet C. Pandey ,  Gurtej S. Sandhu

IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L29/08

Abstract: Some embodiments include an integrated assembly which has a semiconductor material with a surface. A first layer is over and directly against the surface. The first layer includes oxygen and a first metal. The relative amount of oxygen to the first metal is less than or equal to an amount sufficient to form stoichiometric metal oxide throughout the first layer. A second metal is over and directly against the first layer. A second layer is over and directly against the second metal. The second layer includes nitrogen and a third metal. Some embodiments include an integrated assembly which has a semiconductor material with a surface. A metal is adjacent the surface and is spaced from the surface by a distance of less than or equal to about 10 Å. There is no metal germanide or metal silicide between the metal and the surface.

公开(公告)号：US10937644B2

公开(公告)日：2021-03-02

申请号：US16506094

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Matthew S. Thorum ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/677 ,  H01L21/311 ,  H01L21/67

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

公开(公告)号：US10923480B2

公开(公告)日：2021-02-16

申请号：US16409010

申请日：2019-05-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Litao Yang ,  Gurtej S. Sandhu ,  Richard J. Hill

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L27/108 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L23/532

Abstract: Systems, apparatuses, and methods related to capacitance reduction in a semiconductor device are described. An example method may include forming an oxide only spacer over a portion of a sense line, formed on a semiconductor substrate, to separate the sense line from a storage node contact region of a semiconductor device and to reduce a capacitance between the sense line and the storage node contact region. The method may further include forming the storage node contact region in an active area of the semiconductor device neighboring the sense line and conductively connecting the sense line to the storage node contact region to enable a storage node to be sensed by the sense line.

公开(公告)号：US10916586B2

公开(公告)日：2021-02-09

申请号：US16124254

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L27/24 ,  H01L27/11578 ,  H01L45/00

Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

公开(公告)号：US10828924B2

公开(公告)日：2020-11-10

申请号：US16004063

申请日：2018-06-08

Applicant: Micron Technology, Inc.

Inventor： Dan B. Millward ,  Gurtej S. Sandhu

IPC: B32B3/10 ,  B41N1/08 ,  B81C99/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/00 ,  B41N3/03 ,  B05D1/28

Abstract: Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.

公开(公告)号：US10825686B2

公开(公告)日：2020-11-03

申请号：US16676793

申请日：2019-11-07

Applicant: Micron Technology, Inc.

Inventor： Matthew S. Thorum ,  Gurtej S. Sandhu

IPC: H01L21/322 ,  H01L21/30 ,  H01L21/67 ,  H01L21/02

Abstract: An example of forming semiconductor devices can include forming a silicon-hydrogen (Si—H) terminated surface on a silicon structure that includes patterned features by exposing the silicon structure to a hydrogen fluoride (HF) containing solution and performing a surface modification via hydrosilylation by exposing the Si—H terminated surface to an alkene and/or an alkyne.

公开(公告)号：US20200295011A1

公开(公告)日：2020-09-17

申请号：US16353343

申请日：2019-03-14

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  John A. Smythe

IPC: H01L27/108

Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.