公开(公告)号：US20240256188A1

公开(公告)日：2024-08-01

申请号：US18634649

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. The primary die can communicate with an external host device and with the secondary dies. In an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. In an example, each of the secondary dies receives the same first command message.

公开(公告)号：US11967373B2

公开(公告)日：2024-04-23

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US11923002B2

公开(公告)日：2024-03-05

申请号：US17869649

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C7/00 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/56 ,  G11C29/50

CPC classification number: G11C11/5642 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/5628 ,  G11C29/50004

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US20230395145A1

公开(公告)日：2023-12-07

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20230333778A1

公开(公告)日：2023-10-19

申请号：US17723773

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. The primary die can communicate with an external host device and with the secondary dies. In an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. In an example, each of the secondary dies receives the same first command message.

公开(公告)号：US11769552B2

公开(公告)日：2023-09-26

申请号：US17556702

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/003 ,  G11C11/1653 ,  G11C11/1659 ,  G11C13/0023

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

公开(公告)号：US11762443B2

公开(公告)日：2023-09-19

申请号：US17725079

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F1/26 ,  G06F13/16

CPC classification number: G06F1/266 ,  G06F13/1668

Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.

公开(公告)号：US20220326753A1

公开(公告)日：2022-10-13

申请号：US17725079

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F1/26 ,  G06F13/16

Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.

公开(公告)号：US11314301B2

公开(公告)日：2022-04-26

申请号：US16733911

申请日：2020-01-03

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F1/26 ,  G06F13/16

Abstract: Methods, systems, and devices for power management of a memory device are described. An apparatus may include a substrate and an input/output (I/O) interface and memory device coupled with the substrate. The I/O interface may communicate with a host device and the memory device may store data associated with the host device. The apparatus may include a power management component for providing one or more supply voltages to the memory device. The power management component may receive input voltages associated with the substrate and provide the supply voltages to the memory device based on the input voltages. The power management component may include a first portion integrated with the memory device and a second portion coupled with the substrate. The first portion may include control circuitry for the power management component and the second portion may include passive components for the power management component.

公开(公告)号：US20220115065A1

公开(公告)日：2022-04-14

申请号：US17556702

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G11C11/16

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.