中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.021 seconds)

    Short program verify recovery with reduced programming disturbance in a memory sub-system
    11.
    发明授权
    Short program verify recovery with reduced programming disturbance in a memory sub-system 有权

    公开(公告)号：US11282582B2

    公开(公告)日：2022-03-22

    申请号：US16946273

    申请日：2020-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

    Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

    UNSELECTED SUB-BLOCK SOURCE LINE AND BIT LINE PRE-CHARGING TO REDUCE READ DISTURB
    12.
    发明申请
    UNSELECTED SUB-BLOCK SOURCE LINE AND BIT LINE PRE-CHARGING TO REDUCE READ DISTURB 有权

    公开(公告)号：US20230024346A1

    公开(公告)日：2023-01-26

    申请号：US17591361

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

    MODIFIED SEEDING SCHEME DURING A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM
    13.
    发明申请
    MODIFIED SEEDING SCHEME DURING A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210391016A1

    公开(公告)日：2021-12-16

    申请号：US16946274

    申请日：2020-06-12

    Applicant: Micron Technology, Inc.

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/12 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

    Abstract: A processing device in a memory system initiates a program operation on the memory device, the program operation comprising a seeding phase. The processing device further causes a seeding voltage to be applied to a string of memory cells in a data block of the memory device during the seeding phase of the program operation and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation.

    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
    14.
    发明申请
    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210202009A1

    公开(公告)日：2021-07-01

    申请号：US16991836

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/08 ,  G11C16/04

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

    Unselected sub-block source line and bit line pre-charging to reduce read disturb
    15.
    发明授权
    Unselected sub-block source line and bit line pre-charging to reduce read disturb 有权

    公开(公告)号：US11894069B2

    公开(公告)日：2024-02-06

    申请号：US17591361

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/30

    Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

    Pre-boosting scheme during a program operation in a memory sub-system
    17.
    发明授权
    Pre-boosting scheme during a program operation in a memory sub-system 有权

    公开(公告)号：US11183245B1

    公开(公告)日：2021-11-23

    申请号：US16910789

    申请日：2020-06-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic causes a second positive pre-boosting voltage to be applied to a second plurality of word lines of the data block during the pre-boosting phase, wherein the second plurality of word lines is adjacent to the first plurality of wordlines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive pre-booting voltage has a lower magnitude than the first positive pre-boosting voltage. The control logic further causes the second positive pre-boosting voltage to be ramped down to a ground voltage during the pre-boosting phase prior to the first positive pre-boosting voltage being ramped down to the ground voltage.

Patent Agency Ranking