公开(公告)号：US20170075613A1

公开(公告)日：2017-03-16

申请号：US15342287

申请日：2016-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G06F12/0846

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 在存储器装置中，标志存储单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

公开(公告)号：US10438672B2

公开(公告)日：2019-10-08

申请号：US16035857

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.

公开(公告)号：US10126967B2

公开(公告)日：2018-11-13

申请号：US15342287

申请日：2016-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

公开(公告)号：US09646702B2

公开(公告)日：2017-05-09

申请号：US14995302

申请日：2016-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.

公开(公告)号：US20160133327A1

公开(公告)日：2016-05-12

申请号：US14995302

申请日：2016-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.

Abstract translation: 存储器件中的偏置方法便于存储器件编程操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的第一串存储器单元被耦合到公共数据线和公共源，其中数据线被偏置到大于电位的电位 在对所选择的存储单元执行的编程操作期间，源偏置。

公开(公告)号：US20160005474A1

公开(公告)日：2016-01-07

申请号：US14857475

申请日：2015-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Haitao Liu ,  Krishna Parat

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

Abstract translation: 一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到 数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压 之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。