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公开(公告)号：US20150243708A1
公开(公告)日：2015-08-27
申请号：US14189490
申请日：2014-02-25
Applicant: MICRON TECHNOLOGY, INC
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 在一个方面，一种制造交叉点存储器阵列的方法包括形成存储单元材料堆，所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料，其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化，其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻，在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料，并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。
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公开(公告)号：US10573689B2
公开(公告)日：2020-02-25
申请号：US16212861
申请日：2018-12-07
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo , Marcello Ravasio
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号：US10367033B2
公开(公告)日：2019-07-30
申请号：US16112570
申请日：2018-08-24
Applicant: Micron Technology, Inc.
Inventor： Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US09640588B2
公开(公告)日：2017-05-02
申请号：US14867185
申请日：2015-09-28
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo , Marcello Ravasio
CPC classification number: H01L27/2427 , H01L27/224 , H01L27/226 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/148 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号：US09257431B2
公开(公告)日：2016-02-09
申请号：US14036788
申请日：2013-09-25
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Andrea Gotti
IPC: H01L27/105 , H01L21/28 , H01L21/3213 , H01L45/00 , H01L27/24 , H01L27/22
CPC classification number: H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
Abstract translation: 提供了存储单元结构及其形成方法。 示例性存储器单元可以包括开关元件和存储元件。 在存储元件和开关元件之间形成中间电极。 在除了存储元件和开关元件之外的位置处，在开关元件或存储元件附近形成外部电极。 中间电极的横向尺寸不同于外部电极的横向尺寸。
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Patent Agency Ranking
公开(公告)号：US09246100B2
公开(公告)日：2016-01-26
申请号：US13949315
申请日：2013-07-24
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini , Gabriel L. Donadio
CPC classification number: H01L27/2481 , G11C5/063 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.
Abstract translation: 本公开包括存储单元阵列结构及其形成方法。 一种这样的阵列包括堆叠结构，其包括在第一导电材料和第二导电材料之间的存储单元。 存储器单元可以包括选择元件和存储元件。 阵列还可以包括位于堆叠结构的边缘处的电惰性堆叠结构。
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公开(公告)号：US20150029775A1
公开(公告)日：2015-01-29
申请号：US13949315
申请日：2013-07-24
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini , Gabriel L. Donadio
CPC classification number: H01L27/2481 , G11C5/063 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.
Abstract translation: 本公开内容包括存储单元阵列结构及其形成方法。 一种这样的阵列包括堆叠结构，其包括在第一导电材料和第二导电材料之间的存储单元。 存储器单元可以包括选择元件和存储元件。 阵列还可以包括位于堆叠结构的边缘处的电惰性堆叠结构。
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公开(公告)号：US10910437B2
公开(公告)日：2021-02-02
申请号：US16420483
申请日：2019-05-23
Applicant: Micron Technology, Inc.
Inventor： Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US20190067372A1
公开(公告)日：2019-02-28
申请号：US16112570
申请日：2018-08-24
Applicant: Micron Technology, Inc.
Inventor： Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
CPC classification number: H01L27/2463 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US10163978B2
公开(公告)日：2018-12-25
申请号：US15479403
申请日：2017-04-05
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo , Marcello Ravasio
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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