公开(公告)号：US11257535B2

公开(公告)日：2022-02-22

申请号：US16936297

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/407

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20210074357A1

公开(公告)日：2021-03-11

申请号：US16953092

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael A. Shore

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/4091 ,  H01L27/11507 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/00 ,  H01L27/11509 ,  H01L27/105

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

公开(公告)号：US10854270B2

公开(公告)日：2020-12-01

申请号：US16522240

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/408

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.

公开(公告)号：US10770127B2

公开(公告)日：2020-09-08

申请号：US16268818

申请日：2019-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/407

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20200251158A1

公开(公告)日：2020-08-06

申请号：US16268818

申请日：2019-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/407 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US09672939B2

公开(公告)日：2017-06-06

申请号：US14518734

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/38 ,  G11C29/36

CPC classification number: G11C29/44 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/883 ,  G11C2229/723

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

公开(公告)号：US20250118351A1

公开(公告)日：2025-04-10

申请号：US18746226

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/4093

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US20240282355A1

公开(公告)日：2024-08-22

申请号：US18649696

申请日：2024-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

公开(公告)号：US11798610B2

公开(公告)日：2023-10-24

申请号：US17347957

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C11/401 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40611 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/40618

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

公开(公告)号：US20210304813A1

公开(公告)日：2021-09-30

申请号：US17347957

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C11/406 ,  G11C11/408

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.