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11.发明授权公开(公告)号：US11989635B2
公开(公告)日：2024-05-21
申请号：US16913582
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Yao Fu , Paul Glendenning , Tommy Tracy, II , Eric Jonas
Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.
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公开(公告)号：US11580055B2
公开(公告)日：2023-02-14
申请号：US17007636
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning , Paul D. Dlugosch
IPC: G06F15/78 , G06N20/00 , G06F9/448 , G06F1/3225 , G06F13/42 , G05B19/045 , G06F3/06
Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.
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公开(公告)号：US20200133893A1
公开(公告)日：2020-04-30
申请号：US16726523
申请日：2019-12-24
Applicant: Micron Technology, Inc.
Inventor： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
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公开(公告)号：US20180089113A1
公开(公告)日：2018-03-29
申请号：US15280611
申请日：2016-09-29
Applicant: Micron Technology, Inc.
Inventor： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
CPC classification number: G06F13/126 , G06F13/287 , G06F13/4022 , G06F13/404 , G06F2213/2802
Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
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公开(公告)号：US09916145B2
公开(公告)日：2018-03-13
申请号：US15049943
申请日：2016-02-22
Applicant: Micron Technology, Inc.
Inventor： Junjuan Xu , Paul Glendenning
CPC classification number: G06F8/447 , G06F8/443 , G06F8/445 , G06F9/4498
Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.
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Patent Agency Ranking
公开(公告)号：US20170255878A1
公开(公告)日：2017-09-07
申请号：US15214188
申请日：2016-07-19
Applicant: Micron Technology, Inc.
Inventor： Yao Fu , Paul Glendenning , Tommy Tracy, II , Eric Jonas
IPC: G06N99/00
Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and to receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.
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公开(公告)号：US20170193351A1
公开(公告)日：2017-07-06
申请号：US14984955
申请日：2015-12-30
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning , Paul D. Dlugosch
CPC classification number: G06K9/00973 , G06N5/02
Abstract: An apparatus includes a state machine lattice. The apparatus also includes a memory. The memory of the apparatus is configured to receive an event vector, such that the event vector includes an indication of a result of data analysis using the state machine lattice. The apparatus further includes a control system. The control system of the apparatus is configured to selectively provide only a portion of the event vector.
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公开(公告)号：US09509312B2
公开(公告)日：2016-11-29
申请号：US14832543
申请日：2015-08-21
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning , Irene Junjuan Xu
IPC: H03K19/177 , H03K19/20 , G05B19/045 , G06F9/44 , G06F17/50 , H03K19/0175 , G06F7/00
CPC classification number: H03K19/17708 , G05B19/045 , G06F7/00 , G06F9/4498 , G06F17/5054 , H03K19/0175 , H03K19/17704 , H03K19/20 , H03K19/21 , Y02T10/82
Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
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公开(公告)号：US20160239440A1
公开(公告)日：2016-08-18
申请号：US15045550
申请日：2016-02-17
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Irene Junjuan Xu , Paul Glendenning
IPC: G06F13/16 , G06F13/12 , G06F13/40 , H04L12/883 , G06F13/42
CPC classification number: G06F13/1673 , G06F9/4498 , G06F13/124 , G06F13/4022 , G06F13/4282 , G06F17/30516 , G06K9/00496 , G06K9/00973 , G06K9/00979 , H04L49/9021
Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.
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公开(公告)号：US20160019034A1
公开(公告)日：2016-01-21
申请号：US14868047
申请日：2015-09-28
Applicant: Micron Technology, Inc.
Inventor： Paul Glendenning , Junjuan Xu
CPC classification number: G06F8/41 , G06F8/427 , G06F8/443 , G06F8/447 , G06F9/4498 , G06F17/5045 , G06F17/5054
Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.
Abstract translation: 描述了编译器的装置，系统和方法。 一个这样的编译器将源代码转换成包括状态之间的状态和转换的自动机，其中自动机中的状态包括对应于专用硬件元件的专用状态。 编译器将自动机转换为网表，并放置和路由网表以提供用于配置目标设备的机器代码。
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