公开(公告)号：US20210109667A1

公开(公告)日：2021-04-15

申请号：US17131842

申请日：2020-12-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carla L. Christensen ,  Avani F. Trivedi ,  Tracy D. Evans

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56

Abstract: Electronic systems might include a plurality of groups of memory cells and a controller for access of the plurality of groups of memory cells that is configured to cause the electronic system to determine whether a reliability of a particular group of memory cells having a particular reliability rank allocated for storing data of a particular data level at a particular memory density is less than a target reliability, and, if so, determine whether the reliability of the particular group of memory cells at a reduced memory density is less than the target reliability, and, in response to determining that the reliability of the particular group of memory cells at the reduced density is less than the target reliability, allocate the particular group of memory cells for storing data of a lower data level and allocate a different group of memory cells for storing data of the particular data level.

公开(公告)号：US20210065820A1

公开(公告)日：2021-03-04

申请号：US16553241

申请日：2019-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Avani F. Trivedi ,  Tracy D. Evans ,  Carla L. Christensen ,  Tomoko Ogura Iwasaki ,  Aparna U. Limaye

IPC: G11C16/30 ,  G11C16/10 ,  G06F13/16

Abstract: Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.

公开(公告)号：US20210056019A1

公开(公告)日：2021-02-25

申请号：US16995356

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Tracy D. Evans ,  Tomoko Ogura Iwasaki ,  Avani F. Trivedi ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0831 ,  G06F11/30 ,  G06F11/07 ,  G06F1/3212

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

公开(公告)号：US20200167087A1

公开(公告)日：2020-05-28

申请号：US16202219

申请日：2018-11-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carla L. Christensen ,  Avani F. Trivedi ,  Tracy D. Evans

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56

Abstract: Methods of operating an electronic system include allocating a group of memory cells of a plurality of groups of memory cells having a particular rank of a plurality of ranks for storing data of a particular data level of a plurality of data levels, determining a need for an additional group of memory cells for storing data of the particular data level, moving or discarding data from a different group of memory cells storing data of a different data level of the plurality of data levels in response to determining the need for the additional group of memory cells for storing data of the particular data level, and allocating the different group of memory cells for storing data of the particular data level.

公开(公告)号：US12167579B2

公开(公告)日：2024-12-10

申请号：US17533225

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Tracy D. Evans ,  Gloria Y. Yang ,  Jiewei Chen ,  Jing Zhou

IPC: H05K7/20 ,  G05B15/02

Abstract: Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

公开(公告)号：US11726908B2

公开(公告)日：2023-08-15

申请号：US17672872

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Tracy D. Evans ,  Tomoko Ogura Iwasaki ,  Avani F. Trivedi ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/0882 ,  G06F1/3212 ,  G06F11/30 ,  G06F11/07 ,  G06F12/0831

CPC classification number: G06F12/0253 ,  G06F1/3212 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0833 ,  G06F12/0882

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

公开(公告)号：US11698742B2

公开(公告)日：2023-07-11

申请号：US17673408

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Aparna U. Limaye ,  Avani F. Trivedi ,  Tomoko Ogura Iwasaki ,  Tracy D. Evans

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/34 ,  G11C16/24 ,  G11C16/04

CPC classification number: G06F3/0647 ,  G06F3/0608 ,  G06F3/0673 ,  G06F12/10 ,  G11C16/24 ,  G11C16/3459 ,  G06F2212/1044 ,  G06F2212/657 ,  G11C16/0483

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.

公开(公告)号：US11676668B2

公开(公告)日：2023-06-13

申请号：US17200959

申请日：2021-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Avani F. Trivedi ,  Tracy D. Evans ,  Carla L. Christensen ,  Tomoko Ogura Iwasaki ,  Aparna U. Limaye

IPC: G11C16/30 ,  G06F13/16 ,  G11C16/10 ,  G11C5/14

CPC classification number: G11C16/30 ,  G06F13/1668 ,  G11C16/10 ,  G11C5/144

Abstract: Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories.

公开(公告)号：US20220172769A1

公开(公告)日：2022-06-02

申请号：US17673302

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

公开(公告)号：US11282567B2

公开(公告)日：2022-03-22

申请号：US16947795

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.