公开(公告)号：US10783980B2

公开(公告)日：2020-09-22

申请号：US15975697

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Vijayakrishna J. Vankayala

IPC: G11C29/42 ,  G06F11/10 ,  G06F11/16 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/16 ,  G11C7/10 ,  G11C29/02 ,  G06F13/16 ,  G11C29/52

Abstract: Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.

公开(公告)号：US20200059235A1

公开(公告)日：2020-02-20

申请号：US16552633

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop

IPC: H03K19/003 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/4074

Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

公开(公告)号：US10269441B1

公开(公告)日：2019-04-23

申请号：US16049411

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C11/24 ,  G11C17/18 ,  H04L9/08 ,  G11C17/16 ,  G11C17/08

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

公开(公告)号：US10127994B1

公开(公告)日：2018-11-13

申请号：US15789167

申请日：2017-10-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C11/24 ,  G11C17/18 ,  H04L9/08 ,  G11C17/16 ,  G11C17/08

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

公开(公告)号：US12183385B2

公开(公告)日：2024-12-31

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4096 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US11996162B2

公开(公告)日：2024-05-28

申请号：US17831251

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Won Joo Yun

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  H03K19/20

CPC classification number: G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  H03K19/20

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

公开(公告)号：US20240062803A1

公开(公告)日：2024-02-22

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20230395105A1

公开(公告)日：2023-12-07

申请号：US17831251

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Won Joo Yun

IPC: G11C7/10 ,  G11C7/22 ,  H03K19/20

CPC classification number: G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  H03K19/20

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

公开(公告)号：US11727979B2

公开(公告)日：2023-08-15

申请号：US17369055

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  William C. Waldrop ,  Vijayakrishna J. Vankayala

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/2254

Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.