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公开(公告)号:US20160099252A1
公开(公告)日:2016-04-07
申请号:US14831011
申请日:2015-08-20
Applicant: Micron Technology, Inc.
Inventor: Luan C. Tran , Hongbin Zhu , John D. Hopkins , Yushi Hu
IPC: H01L27/115
CPC classification number: H01L27/11556 , H01L21/823412 , H01L21/823487 , H01L21/823885 , H01L27/11582 , H01L29/7827
Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
Abstract translation: 本公开包括具有连续信道的存储器及其处理方法。 许多实施例包括形成具有串联连接在源选择栅极和漏极选择栅极之间的存储单元的垂直堆叠,其中形成垂直堆叠包括形成用于源选择栅极,存储器单元和漏极选择的连续沟道 栅极,并且去除用于漏极选择栅极的连续沟道的一部分,使得连续沟道对于漏极选择栅极比对于存储器单元和源选择栅极更薄。
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公开(公告)号:US20150333143A1
公开(公告)日:2015-11-19
申请号:US14281569
申请日:2014-05-19
Applicant: Micron Technology, Inc.
Inventor: John M. Meldrim , Yushi Hu , Rita J. Klein , John D. Hopkins , Hongbin Zhu , Gordon A. Haller , Luan C. Tran
IPC: H01L29/49 , H01L21/28 , H01L27/115
CPC classification number: H01L27/11582 , H01L21/28097 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/4975
Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠,并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下,并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料,并且直接抵抗金属硅化物,导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。
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公开(公告)号:US11658033B2
公开(公告)日:2023-05-23
申请号:US16950115
申请日:2020-11-17
Applicant: Micron Technology, Inc.
IPC: H01L21/225 , H01L21/28 , H01L27/11556 , H01L27/11582
CPC classification number: H01L21/2253 , H01L21/28 , H01L27/11556 , H01L27/11582 , H01L29/40114 , H01L29/40117
Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.
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公开(公告)号:US11315941B2
公开(公告)日:2022-04-26
申请号:US16291453
申请日:2019-03-04
Applicant: Micron Technology, Inc.
Inventor: Luan C. Tran , Hongbin Zhu , John D. Hopkins , Yushi Hu
IPC: H01L27/11556 , H01L21/8234 , H01L21/8238 , H01L27/11582 , H01L29/78
Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
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公开(公告)号:US10943920B2
公开(公告)日:2021-03-09
申请号:US16738499
申请日:2020-01-09
Applicant: Micron Technology, Inc.
Inventor: John M. Meldrim , Yushi Hu , Rita J. Klein , John D. Hopkins , Hongbin Zhu , Gordon A. Haller , Luan C. Tran
IPC: H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/28 , H01L29/49
Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
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公开(公告)号:US20200152658A1
公开(公告)日:2020-05-14
申请号:US16738499
申请日:2020-01-09
Applicant: Micron Technology, Inc.
Inventor: John M. Meldrim , Yushi Hu , Rita J. Klein , John D. Hopkins , Hongbin Zhu , Gordon A. Haller , Luan C. Tran
IPC: H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/28 , H01L29/49
Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
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公开(公告)号:US10553611B2
公开(公告)日:2020-02-04
申请号:US16413498
申请日:2019-05-15
Applicant: Micron Technology, Inc.
Inventor: John M. Meldrim , Yushi Hu , Rita J. Klein , John D. Hopkins , Hongbin Zhu , Gordon A. Haller , Luan C. Tran
IPC: H01L27/11556 , H01L27/11582 , H01L27/11524 , H01L27/1157 , H01L21/28 , H01L29/49
Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
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公开(公告)号:US10355018B1
公开(公告)日:2019-07-16
申请号:US16290169
申请日:2019-03-01
Applicant: Micron Technology, Inc.
Inventor: Justin B. Dorhout , David Daycock , Kunal R. Parekh , Martin C. Roberts , Yushi Hu
IPC: H01L27/088 , H01L21/336 , H01L27/11582 , H01L29/66 , H01L29/78 , H01L29/76
Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
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公开(公告)号:US20190198516A1
公开(公告)日:2019-06-27
申请号:US16291453
申请日:2019-03-04
Applicant: Micron Technology, Inc.
Inventor: Luan C. Tran , Hongbin Zhu , John D. Hopkins , Yushi Hu
IPC: H01L27/11556 , H01L21/8234 , H01L29/78 , H01L21/8238
CPC classification number: H01L27/11556 , H01L21/823412 , H01L21/823487 , H01L21/823885 , H01L27/11582 , H01L29/7827
Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
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公开(公告)号:US10147727B2
公开(公告)日:2018-12-04
申请号:US15895587
申请日:2018-02-13
Applicant: Micron Technology, Inc.
Inventor: Jaydeb Goswami , Zailong Bian , Yushi Hu , Eric R. Blomiley , Jaydip Guha , Thomas Gehrke
IPC: H01L27/108 , H01L29/423 , H01L29/08 , H01L29/49 , H01L23/532 , H01L23/528
Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
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