-
公开(公告)号：US20220261153A1
公开(公告)日：2022-08-18
申请号：US17580296
申请日：2022-01-20
Applicant: Micron Technology, Inc.
Inventor： Paolo Papa , Luigi Esposito , Massimo Iaculo , Giuseppe D'Eliseo , Alberto Sassara , Carminantonio Manganelli , Salvatore Del Prete
Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.
-
公开(公告)号：US20220188018A1
公开(公告)日：2022-06-16
申请号：US17688304
申请日：2022-03-07
Applicant: Micron Technology, Inc.
Inventor： Eric Kwok Fung Yuen , Giuseppe Ferrari , Massimo Iaculo , Lalla Fatima Drissi , Xinghui Duan , Giuseppe D'Eliseo
Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.
-
公开(公告)号：US20210141557A1
公开(公告)日：2021-05-13
申请号：US16075464
申请日：2017-12-21
Applicant: MICRON TECHNOLOGY INC.
Inventor： Eric Kwok Fung Yuen , Giuseppe Ferrari , Massimo Iaculo , Lalla Fatima Drissi , Xinghui Duan , Giuseppe D'Eliseo
IPC: G06F3/06
Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.
-
公开(公告)号：US10983918B2
公开(公告)日：2021-04-20
申请号：US16294427
申请日：2019-03-06
Applicant: Micron Technology, Inc.
Inventor： Carminantonio Manganelli , Yoav Weinberg , Alberto Sassara , Paolo Papa , Luigi Esposito , Giuseppe D'Eliseo , Angelo Della Monica , Massimo Iaculo
IPC: G06F12/1009
Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.
-
公开(公告)号：US10725904B2
公开(公告)日：2020-07-28
申请号：US16075543
申请日：2017-12-13
Applicant: Micron Technology, Inc.
Inventor： Zhao Cui , Eric Kwok Fung Yuen , Guan Zhong Wang , Xinghui Duan , Giuseppe D'Eliseo , Giuseppe Ferrari
IPC: G06F12/02 , G06F12/0873
Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.
-
Patent Agency Ranking
公开(公告)号：US20200210344A1
公开(公告)日：2020-07-02
申请号：US16294427
申请日：2019-03-06
Applicant: Micron Technology, Inc.
Inventor： Carminantonio Manganelli , Yoav Weinberg , Alberto Sassara , Paolo Papa , Luigi Esposito , Giuseppe D'Eliseo , Angelo Della Monica , Massimo Iaculo
IPC: G06F12/1009
Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.
-
公开(公告)号：US12277979B2
公开(公告)日：2025-04-15
申请号：US18527978
申请日：2023-12-04
Applicant: Micron Technology, Inc.
Inventor： Carminantonio Manganelli , Paolo Papa , Massimo Iaculo , Giuseppe D'Eliseo , Alberto Sassara
Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
-
公开(公告)号：US20240272832A1
公开(公告)日：2024-08-15
申请号：US18586207
申请日：2024-02-23
Applicant: Micron Technology, Inc.
Inventor： Alberto Sassara , Giuseppe D'Eliseo , Lalla Fatima Drissi , Luigi Esposito , Paolo Papa , Salvatore Del Prete , Xiangang Luo , Xiaolai Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679
Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.
-
公开(公告)号：US20230376245A1
公开(公告)日：2023-11-23
申请号：US17750131
申请日：2022-05-20
Applicant: Micron Technology, Inc.
Inventor： Alberto Sassara , Giuseppe D'Eliseo , Lalla Fatima Drissi , Luigi Esposito , Paolo Papa , Salvatore Del Prete , Xiangang Luo , Xiaolai Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679
Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.
-
公开(公告)号：US11663120B2
公开(公告)日：2023-05-30
申请号：US17521340
申请日：2021-11-08
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
CPC classification number: G06F12/0246 , G06F12/0253 , G06F12/0292 , G11C16/10 , G06F2212/7201 , G06F2212/7205
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
-
-
-
-
-
-
-
-
-
Search Results
57
records
(took 0.025 seconds)
