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公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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公开(公告)号：US07317777B2
公开(公告)日：2008-01-08
申请号：US10265759
申请日：2002-10-07
IPC分类号： H04L25/00
CPC分类号： H03L7/091 , H04L7/0337
摘要： A system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter and may contain relatively long periods of successive univalue data bits. The method includes digitally sampling a received data stream at predefined intervals to produce a data set; estimating when logic transitions occur in the data set; detecting a timing trend represented by the estimated logic transitions; and adjusting a frequency of the first clock so that the timing trend averages approximately zero over a plurality of logic transitions.
摘要翻译： 用于跟踪/调整可能包含大量噪声和/或抖动的输入串行数据流中的相位或频率变化的系统和方法，并且可以包含相对较长的连续的单值数据位。 该方法包括以预定的间隔对接收的数据流进行数字采样以产生数据集; 在数据集中发生逻辑转换时估计; 检测由所估计的逻辑转换表示的定时趋势; 以及调整所述第一时钟的频率，使得所述时序趋势在多个逻辑转换中平均为零。
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13.发明授权公开(公告)号：US08587464B2
公开(公告)日：2013-11-19
申请号：US13346242
申请日：2012-01-09
IPC分类号： H03M1/12
CPC分类号： H03M1/182 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.
摘要翻译： 时间交织的模数转换器（ADC）包括多个ADC块，每个ADC块包括：至少一个ADC单元，被配置为将模拟输入转换成数字输出; 以及数字增益控制器，被配置为基于所述至少一个ADC单元的实际输出与所述至少一个ADC单元的预期输出的比较来调整所述至少一个ADC单元的参考电压。
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14.发明授权Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US08054926B2
公开(公告)日：2011-11-08
申请号：US12116151
申请日：2008-05-06
IPC分类号： H04L7/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.
摘要翻译： 基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟触发的接收数据的数据锁存器。 该系统还包括一个错误确定单元，用于确定哪个采样的接收数据是错误的，并且用于产生一个相位/频率校正信号。 此外，该系统包括用于根据校正信号产生采样时钟的时钟发生器。
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公开(公告)号：US07934115B2
公开(公告)日：2011-04-26
申请号：US12332396
申请日：2008-12-11
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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16.发明授权One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效单采样每位决策反馈均衡器（DFE）时钟和数据恢复公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。
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公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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18.发明授权method for providing automatic adaptation to frequency offsets in high speed serial links 有权用于在高速串行链路中提供自动适应频率偏移的方法公开(公告)号：US07477713B2
公开(公告)日：2009-01-13
申请号：US10791175
申请日：2004-03-02
申请人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L7/02
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。
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公开(公告)号：US09473333B2
公开(公告)日：2016-10-18
申请号：US12028953
申请日：2008-02-11
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译： 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。
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20.发明授权公开(公告)号：US08436677B2
公开(公告)日：2013-05-07
申请号：US12966624
申请日：2010-12-13
申请人： Lukas Kull , Martin L. Schmatz
发明人： Lukas Kull , Martin L. Schmatz
CPC分类号： G11C5/147 , H03M1/0863 , H03M1/12
摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.
摘要翻译： 为参考电压发生器提供了一种设计结构。 该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。 第一个电容为模数转换器提供电压参考。 控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。
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