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1.发明授权Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US08054926B2
公开(公告)日：2011-11-08
申请号：US12116151
申请日：2008-05-06
IPC分类号： H04L7/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.
摘要翻译： 基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟触发的接收数据的数据锁存器。 该系统还包括一个错误确定单元，用于确定哪个采样的接收数据是错误的，并且用于产生一个相位/频率校正信号。 此外，该系统包括用于根据校正信号产生采样时钟的时钟发生器。
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2.发明授权Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US07522687B2
公开(公告)日：2009-04-21
申请号：US11214161
申请日：2005-08-29
IPC分类号： H04L7/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).
摘要翻译： 根据本发明的基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟（sclk）触发的接收数据的数据锁存器（16）。 该系统还包括用于确定采样的接收数据是否以及哪个是错误的并且用于产生相位/频率校正信号（ctrl）的错误确定单元（20,21）。 此外，该系统包括用于根据校正信号（ctrl）产生采样时钟（sclk）的时钟发生器（23,24,25）。
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公开(公告)号：US07692447B2
公开(公告)日：2010-04-06
申请号：US12115933
申请日：2008-05-06
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K17/164 , H04L25/0278 , H04L25/028
摘要： A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.
摘要翻译： 提供了驱动器电路，其包括至少两个相等的主单元（MU），每个主单元包括耦合到数据输出（dout）的至少两个子单元（SU）。 每个子单元（SU）适于表示相应的预定阻抗。 每个主单元（MU）适于当处于数据模式时，根据要发送的数据信号，各个主单元（MU）的每个子单元（SU）可切换到第一或第二参考电位。 每个主单元（MU）还适用于当处于终止模式时，相应主单元（MU）的子单元（SU）被切换到第一或第二参考电位，使得各个主单元（MU）的输出 单位（MU）相对于第一或第二参考电位的数据输出（dout）的驱动是中性的。
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公开(公告)号：US07893766B1
公开(公告)日：2011-02-22
申请号：US12557139
申请日：2009-09-10
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45632 , H03F2203/45008 , H03F2203/45078 , H03F2203/45292 , H03F2203/45342
摘要： A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.
摘要翻译： 一种用于扩展差分放大器的共模范围的方法和装置。 电路具有共模检测电路，共模电压反相电路和差分放大器。 共模检测电路接收差分信号并检测共模电压。 共模电压反相电路耦合到共模检测电路。 共模电压反相电路具有接收共模电压的输入节点和输出体电压的输出节点，其中共模电压反相电路在共模电压和体电压之间产生反向关系。 差分放大器包括具有耦合到共模电压反相电路的输出节点的一对主体端子的差分对晶体管。
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公开(公告)号：US07684517B2
公开(公告)日：2010-03-23
申请号：US12045343
申请日：2008-03-10
IPC分类号： H04L27/00
摘要： Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.
摘要翻译： 实施例包括分时检测器，其被设计为能够以指定的模式与第一参考电压和第二参考电压相对于串行数据传输进行比较。 在许多实施例中，图案是预定义的，并且在一些实施例中，图案包括重叠周期。 在重叠期间，将第一和第二参考电压与数据传输进行比较，以确定是否可以检测有效数据。 在基于参考电压之一检测到有效位时，产生输出信号以指示数据传输包括有效数据信号。 有利地，比较之间的交替可以降低功耗。 在许多实施例中，取决于指定的模式，功率降低可以是例如50％。
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公开(公告)号：US07339390B2
公开(公告)日：2008-03-04
申请号：US11140765
申请日：2005-05-31
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
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公开(公告)号：US08130887B2
公开(公告)日：2012-03-06
申请号：US12124106
申请日：2008-05-20
申请人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US06970529B2
公开(公告)日：2005-11-29
申请号：US09996113
申请日：2001-11-28
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
摘要翻译： 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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9.发明授权公开(公告)号：US06717997B1
公开(公告)日：2004-04-06
申请号：US09204025
申请日：1998-12-01
IPC分类号： H04L700
CPC分类号： H03L7/0805 , H03K5/133 , H03K2005/00019 , H03L7/0995
摘要： In an electronic system such as a communications integrated circuit including a plurality of components, e.g., transmitters, each of which are operative to demand current responsive to a control signal applied thereto, an apparatus for time-distributing current demand comprises a first phase control circuit configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of components, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal. In an embodiment, the first phase control circuit comprises a ring oscillator including a first string of delay circuits operative to produce a plurality of output signals that are phased with respect to one another according to a phase control signal applied thereto. A loop control circuit is configured to receive a reference clock signal and an output signal from a delay circuit of the ring oscillator and operative to produce the phase control signal therefrom. The plurality of second phase control circuits may comprise a second string of delay circuits, e.g., delay circuits such as those in the first string. Fine phase granularity and stable signal phasing can thereby be provided. Related operating methods are also described.
摘要翻译： 在诸如包括多个组件（例如发射机）的通信集成电路的电子系统中，每个都可以响应于施加到其上的控制信号而要求电流，用于时分布电流需求的装置包括第一相位控制电路 被配置为接收参考时钟信号并且用于从其产生同步的输出信号，所述第一相位控制电路产生用于使输出信号与参考时钟信号同步的相位控制信号。 多个第二相位控制电路响应于至少一个输入控制信号和相位控制信号，并且可操作以将多个相控输出控制信号施加到多个分量，相控相输出控制信号相对于彼此分阶段 通过依赖于相位控制信号的时间间隔。 在一个实施例中，第一相位控制电路包括环形振荡器，该环形振荡器包括第一串延迟电路，其可操作以根据施加到其上的相位控制信号产生相对于彼此相位的多个输出信号。 环路控制电路被配置为从环形振荡器的延迟电路接收参考时钟信号和输出信号，并且用于从其产生相位控制信号。 多个第二相位控制电路可以包括第二串延迟电路，例如延迟电路，例如第一串中的延迟电路。 从而可以提供细相粒度和稳定的信号定相。 还描述了相关的操作方法。
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公开(公告)号：US5942999A
公开(公告)日：1999-08-24
申请号：US910956
申请日：1997-08-08
CPC分类号： H03M1/0604 , H03M1/742
摘要： An integrated D/A converter has a first feedback circuit for generating a first bias voltage to compensate for systemic changes. A second feedback circuit includes a plurality of switchable current sources biased by the first bias voltage and controlled by an externally supplied attenuation control signal to generate a second bias voltage which is applied to control the D/A current sources.
摘要翻译： 集成D / A转换器具有用于产生第一偏置电压以补偿系统变化的第一反馈电路。 第二反馈电路包括由第一偏置电压偏置并由外部提供的衰减控制信号控制的多个可切换电流源，以产生用于控制D / A电流源的第二偏置电压。
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