公开(公告)号：US5844836A

公开(公告)日：1998-12-01

申请号：US822518

申请日：1997-03-24

申请人： Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

发明人： Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

摘要翻译： 在存储节点处具有增加的单元电容的静态随机存取存储器（SRAM）单元利用电容结构。 电容结构包括多晶硅导电线与钨局部互连之间的电介质材料。 多晶硅板各自连接到与SRAM单元相关联的横向晶体管的漏极。 可以在局部互连和多晶硅导电线之间沉积诸如二氧化硅的电介质材料。 电容器结构设置在与SRAM单元相关联的第一和第二N沟道下拉晶体管之间。

公开(公告)号：US5796651A

公开(公告)日：1998-08-18

申请号：US858589

申请日：1997-05-19

申请人： Stephen C. Horne ,  Richard K. Klein ,  Asim A. Selcuk ,  Nicholas John Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst

发明人： Stephen C. Horne ,  Richard K. Klein ,  Asim A. Selcuk ,  Nicholas John Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst

IPC分类号： G11C8/08 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C11/418 ,  G11C8/08

摘要： A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.

摘要翻译： 存储器件在读取操作期间使用减少的字线电压。 存储器件包括存储单元和用于访问单元的通过晶体管。 该单元包括耦合到具有与传输晶体管基本相同的导电性的下拉晶体管的存储节点。 驱动电路在读取操作期间产生降低的字线电压以激活传输晶体管。 减小的字线电压具有小于用于激活下拉晶体管的偏置电压的幅度的幅度。

公开(公告)号：US5646448A

公开(公告)日：1997-07-08

申请号：US699821

申请日：1996-08-19

申请人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

发明人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

摘要翻译： 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

公开(公告)号：US5627110A

公开(公告)日：1997-05-06

申请号：US327757

申请日：1994-10-24

申请人： Raymond T. Lee ,  Richard K. Klein

发明人： Raymond T. Lee ,  Richard K. Klein

IPC分类号： H01L21/3105 ,  H01L21/465

CPC分类号： H01L21/31053 ,  Y10S438/942 ,  Y10S438/975

摘要： A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prior to metal deposition. The method comprises (a) depositing a first removable layer on the wafer; (b) removing a portion of the first removable layer to form a large window around the first topographical mark and to retain an area of the first removable layer around the window; (c) forming an island of material within the: window and over the first topographical mark, wherein the island having a top surface of a second topographical mark replicating the first topographical mark; (d) depositing a second removable layer over the wafer including over the area and the island; (e) chemical-mechanical polishing the second removable layer to substantially planarize the second removable layer; and (f) removing the second removable layer deposited over the area and the island to expose the second topographical mark. The outer dimension of the window is large enough so that the upper surface of the second topographical mark and the upper surface of the material located in the remaining area on the wafer are of approximately equal spacing from the substantially planarized second removable layer. Accordingly, additional window mask process can be eliminated because one etch process, such as a contact etch, will be sufficient to expose the second topographical mark.

摘要翻译： 当化学机械抛光平面化技术用于在金属沉积之前基本上平坦化晶片的表面时，制造半导体器件的方法消除了使用额外的窗口掩模工艺来在晶片上暴露诸如对准靶之类的地形标记的需要 。 该方法包括（a）在晶片上沉积第一可移除层; （b）去除所述第一可移除层的一部分以在所述第一外形标记周围形成大窗口并且保持所述第一可移除层的周围所述窗口的区域; （c）在所述窗口内和所述第一地形标记之上形成材料岛，其中所述岛具有复制所述第一地形标记的第二地形标记的顶表面; （d）在所述晶片上沉积包括所述区域和所述岛上的第二可移除层; （e）化学机械抛光第二可移除层以基本上平坦化第二可移除层; 和（f）去除沉积在区域和岛上的第二可移除层以暴露第二外形标记。 窗口的外部尺寸足够大，使得第二外形标记的上表面和位于晶片上的剩余区域中的材料的上表面距离基本上平坦化的第二可移除层大致相等。 因此，可以消除附加的窗口掩模处理，因为诸如接触蚀刻的一个蚀刻工艺将足以暴露第二外形标记。

公开(公告)号：US06535015B1

公开(公告)日：2003-03-18

申请号：US09845266

申请日：2001-04-30

申请人： Srinath Krishnan ,  Dong-Hyuk Ju ,  William G. En ,  Siu Lun Lee ,  Richard K. Klein

发明人： Srinath Krishnan ,  Dong-Hyuk Ju ,  William G. En ,  Siu Lun Lee ,  Richard K. Klein

IPC分类号： G01R3102

CPC分类号： G01R31/2884

摘要： An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

摘要翻译： 用于绝缘体上硅电路结构的集成测试电路形成在与电路结构相同的晶片上。 晶片包括耦合到绝缘体上硅电路结构的输入电路，其产生用于操作绝缘体上硅电路结构的驱动信号，以及输出电路，其处理来自电路结构的响应信号，以产生表示某些特性的输出信号 硅绝缘体电路结构。

公开(公告)号：US6046088A

公开(公告)日：2000-04-04

申请号：US985400

申请日：1997-12-05

申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

申请人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

发明人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

摘要翻译： 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US4912540A

公开(公告)日：1990-03-27

申请号：US230696

申请日：1988-08-05

申请人： Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

发明人： Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

IPC分类号： H01L21/768 ,  H01L29/04 ,  H01L23/48 ,  H01L29/34

CPC分类号： H01L21/76895 ,  H01L21/7684 ,  H01L21/76877

摘要： A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.

摘要翻译： 提供了减小面积对接接触结构（10'），其特别适用于四晶体管静态RAM单元。 形成了包括掺杂硅区域和位于其上方的一层或多层多晶硅和氧化物的结构，其中一层多晶硅可以是栅极多晶硅。 然后通过所有上层进行各向异性蚀刻，所述上层包括可能存在的任何上多晶硅层，但在掺杂硅区域和存在的任何栅多晶硅层停止以形成接触孔（26'）。 接触孔填充有诸如钨或多晶硅的材料的导电插塞（32）并被回蚀。 在任一种情况下，与存在的所有多晶硅层和掺杂的硅区域接触。 在各向异性蚀刻工艺中，采用两步蚀刻。 第一蚀刻对于材料是非特异性的，以基本上相同的速率蚀刻所有相关材料（多晶硅和氧化物）并且继续通过任何上多晶硅层，但是在蚀刻掺杂硅区域或任何栅极多晶硅层之前终止 22）。 第二蚀刻对于材料是特定的，比多晶硅或硅更快地蚀刻二氧化硅，因此停止在栅极多晶硅层和掺杂的硅区域。

公开(公告)号：US6146954A

公开(公告)日：2000-11-14

申请号：US119934

申请日：1998-07-21

申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417

CPC分类号： H01L29/66545 ,  H01L21/2257 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783

摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.

摘要翻译： 一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在FET之前和之后制造FET和局部互连件的源极和漏极来形成多晶硅栅极和局部互连之间的最小绝缘空间 形成FET的栅极。 在形成栅极之前去除源极和漏极之间的绝缘层的一部分。 优选地，在该方法中使用在绝缘层下方的半导体衬底上的蚀刻停止层。

公开(公告)号：US6051881A

公开(公告)日：2000-04-18

申请号：US986097

申请日：1997-12-05

申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC分类号： H01L23/522 ,  H01L23/535 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/20 ,  H01L21/7681 ,  H01L21/76895 ,  H01L27/0676

摘要： A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

摘要翻译： 一种方法和所得到的器件，通过在多晶硅栅极上形成绝缘层，并利用蚀刻阻挡层保护所选择的栅极和绝缘层，从而允许在多晶硅栅极之间形成最小的绝缘空间，从而局部互连金属化的开口可以 不对准，并且所选择的门将被其蚀刻屏障保护，并且不暴露于开口。 此外，局部互连导电材料可以通过栅极或不相关的电阻器，而不会使栅极/电阻器短路。