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    Method for self-aligning polysilicon gates with field isolation and the resultant structure
    2.
    发明授权
    Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
    使用场隔离自对准多晶硅栅极的方法及其结果

    公开(公告)号：US6046088A

    公开(公告)日：2000-04-04

    申请号：US985400

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

    摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

    摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

    Memory cell for storing at least three logic states
    7.
    发明授权
    Memory cell for storing at least three logic states 失效
    用于存储至少三个逻辑状态的存储单元

    公开(公告)号：US5889697A

    公开(公告)日：1999-03-30

    申请号：US947123

    申请日：1997-10-08

    申请人： Asim A. Selcuk ,  Craig S. Sander

    发明人： Asim A. Selcuk ,  Craig S. Sander

    IPC分类号： G11C11/56 ,  G11C11/00

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/3431 ,  G11C11/412

    摘要： A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the pair of storage nodes. To store a third logic state, the third-level storage and refresh circuitry maintain the multi-level signals at both storage nodes at substantially equal intermediate levels.

    摘要翻译： 用于存储具有至少三个逻辑状态的数据的存储单元包括耦合到一对存储节点的一对存储设备和第三级存储和刷新电路。 存储设备保持表示该对存储节点处的第一和第二逻辑状态的多电平信号。 为了存储第三逻辑状态，第三级存储和刷新电路在两个存储节点处维持基本相等的中间级的多级信号。

    Reduced area butting contact structure
    8.
    发明授权
    Reduced area butting contact structure 失效
    减少对接接触结构

    公开(公告)号：US4912540A

    公开(公告)日：1990-03-27

    申请号：US230696

    申请日：1988-08-05

    申请人： Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

    发明人： Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

    IPC分类号： H01L21/768 ,  H01L29/04 ,  H01L23/48 ,  H01L29/34

    CPC分类号： H01L21/76895 ,  H01L21/7684 ,  H01L21/76877

    摘要： A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.

    摘要翻译： 提供了减小面积对接接触结构（10'），其特别适用于四晶体管静态RAM单元。 形成了包括掺杂硅区域和位于其上方的一层或多层多晶硅和氧化物的结构，其中一层多晶硅可以是栅极多晶硅。 然后通过所有上层进行各向异性蚀刻，所述上层包括可能存在的任何上多晶硅层，但在掺杂硅区域和存在的任何栅多晶硅层停止以形成接触孔（26'）。 接触孔填充有诸如钨或多晶硅的材料的导电插塞（32）并被回蚀。 在任一种情况下，与存在的所有多晶硅层和掺杂的硅区域接触。 在各向异性蚀刻工艺中，采用两步蚀刻。 第一蚀刻对于材料是非特异性的，以基本上相同的速率蚀刻所有相关材料（多晶硅和氧化物）并且继续通过任何上多晶硅层，但是在蚀刻掺杂硅区域或任何栅极多晶硅层之前终止 22）。 第二蚀刻对于材料是特定的，比多晶硅或硅更快地蚀刻二氧化硅，因此停止在栅极多晶硅层和掺杂的硅区域。

    Contact plug and interconnect employing a barrier lining and a backfilled conductor material
    9.
    发明授权
    Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
    使用阻挡衬里和回填导体材料的接触插头和互连

    公开(公告)号：US4960732A

    公开(公告)日：1990-10-02

    申请号：US436399

    申请日：1989-11-14

    申请人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    发明人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

    摘要翻译： 在通过绝缘层（14）的接触孔（16）中形成稳定的低电阻接触，所述绝缘层（例如，二氧化硅）形成在半导体衬底（12）（例如硅）的表面上， 区域（10）。 触点包括（a）沿着绝缘层的壁形成并与掺杂区域的部分接触的钛的粘合和接触层（18）; （b）形成在粘附和接触层上的阻挡层（20）; 和（c）导电材料（22），其形成在所述阻挡层上并且至少基本上填充所述接触孔。 图案化金属层（26）与其它器件和外部电路形成欧姆接触互连。 粘附和接触层和阻挡层物理或化学气相沉积到氧化物表面上。 导电层包括CVD或偏置溅射的钨，钼或原位掺杂的CVD多晶硅中的一种。 本发明的接触避免了在与其它接触方案相关联的氧化物 - 硅界面和蠕虫孔上侵占的问题，但是保持了工艺简单性。

    Triple-poly 4T static ram cell with two independent transistor gates
    10.
    发明授权
    Triple-poly 4T static ram cell with two independent transistor gates 失效
    具有两个独立晶体管栅极的三聚四极静态柱塞电池

    公开(公告)号：US4951112A

    公开(公告)日：1990-08-21

    申请号：US280782

    申请日：1988-12-07

    申请人： Tat C. Choi ,  Richard K. Klein ,  Craig S. Sander

    发明人： Tat C. Choi ,  Richard K. Klein ,  Craig S. Sander

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1112 ,  Y10S257/904

    摘要： A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.

    摘要翻译： 包括具有两个下拉晶体管（18,20）和两个通过栅晶体管（12,14）的触发器的4T静态RAM单元（10）通过采用两个单独的栅极氧化物层（74,76）和相关联的 分离的多晶硅沉积物（52a-b，56）。 两个缩小区域触点（58,60）连接到电路（10）的节点（26,30）。 减小面积对接触点包括垂直布置的掺杂多晶硅插塞（94），其在底层中与埋入的多晶硅层（负载聚合物88，栅极聚合物52a）和掺杂的硅区域（80）电互连。 为下拉和栅极晶体管添加形成单独的栅极氧化物的处理步骤导致更小的单元面积，并将触点的要求从三个减少到两个。 此外，单独的栅极氧化允许下拉和栅极晶体管的独立优化。