公开(公告)号：US06841836B2

公开(公告)日：2005-01-11

申请号：US10738952

申请日：2003-12-16

申请人： Mario Saggio ,  Ferruccio Frisina

发明人： Mario Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.

公开(公告)号：US09018635B2

公开(公告)日：2015-04-28

申请号：US13221778

申请日：2011-08-30

申请人： Ferruccio Frisina ,  Angelo Magri' ,  Mario Giuseppe Saggio

发明人： Ferruccio Frisina ,  Angelo Magri' ,  Mario Giuseppe Saggio

IPC分类号： H01L29/16 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/66666 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/402 ,  H01L29/66431 ,  H01L29/7811 ,  H01L29/7813

摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

摘要翻译： 一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

公开(公告)号：US20120187480A1

公开(公告)日：2012-07-26

申请号：US13434741

申请日：2012-03-29

申请人： Alfio Guarnera ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

发明人： Alfio Guarnera ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC分类号： H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/2003 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

摘要翻译： 用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。 掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

公开(公告)号：US07304335B2

公开(公告)日：2007-12-04

申请号：US11279967

申请日：2006-04-17

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US07067363B2

公开(公告)日：2006-06-27

申请号：US10749134

申请日：2003-12-30

申请人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/337 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US06809383B2

公开(公告)日：2004-10-26

申请号：US09925080

申请日：2001-08-08

申请人： Ferruccio Frisina

发明人： Ferruccio Frisina

IPC分类号： H01L2974

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/66712 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers. The second step up to the sixth step are repeated at least one time in order to form a final edge structure including a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers and formed by superimposition of the doped regions subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther from the high voltage semiconductor device.

摘要翻译： 制造高压半导体器件的边缘结构的方法，包括形成第一导电类型的第一半导体层的第一步骤，在第一半导体层的顶表面上形成第一掩模的第二步骤，第三步骤 去除所述第一掩模的部分以在其中形成至少一个开口;第四步骤，通过所述至少一个开口在所述第一半导体层中引入第二导电类型的掺杂剂;第五步骤，完全去除所述第一掩模 以及在第一半导体层上形成第一导电类型的第二半导体层，第六步骤，在第一半导体层和第二半导体层中形成第二导电类型的掺杂区， 。 至少第一步的第二步重复至少一次以便形成最终边缘结构，其包括多个第一导电类型的叠加半导体层和至少两列第二导电类型的掺杂区域，列 以叠加的半导体层的数量插入并且通过随后通过掩模开口注入的掺杂区的叠加而形成，高压半导体器件附近的列比离高压半导体器件更远的列深。

公开(公告)号：US06365931B1

公开(公告)日：2002-04-02

申请号：US09412475

申请日：1999-10-05

申请人： Ferruccio Frisina ,  Giuseppe Ferla

发明人： Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  G11C29/14 ,  G11C29/50 ,  G11C2029/0403 ,  H01L21/76202 ,  H01L21/8238 ,  H01L29/6656 ,  H01L29/66712

摘要： Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

摘要翻译： 半导体功率器件包括第一导电类型的半导体层，其中形成包括第一导电类型的源极区的第二导电类型的体区，与半导体层重叠的栅极氧化层， 主体区域，叠加到栅极氧化物层的多晶硅区域和叠加到多晶硅区域的第一绝缘材料的区域。 该器件包括位于两个多晶硅区域和第一绝缘材料的区域的一侧上的第二绝缘材料的区域，以及位于主体区域上的开口附近的栅极氧化物层的区域，位于多晶硅区域之间的氧化物区域 以及第二绝缘材料的区域，叠加到第二绝缘材料的区域的氧化物间隔物。

公开(公告)号：US06228719B1

公开(公告)日：2001-05-08

申请号：US09235067

申请日：1999-01-21

申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/66712

摘要： A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

摘要翻译： MOS门控功率器件包括多个基本功能单元，每个基本功能单元包括形成在具有第一电阻率值的第二导电类型的半导体材料层中的第一导电类型的体区。 在每个体区下方提供具有高于第一电阻率值的第二电阻率值的第二导电类型的相应轻掺杂区。

公开(公告)号：US5939769A

公开(公告)日：1999-08-17

申请号：US904257

申请日：1997-07-31

申请人： Ferruccio Frisina ,  Salvatore Coffa

发明人： Ferruccio Frisina ,  Salvatore Coffa

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66295 ,  H01L29/0615 ,  H01L29/167 ,  H01L29/73 ,  Y10S148/01 ,  Y10S438/965

摘要： There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.

摘要翻译： 描述了在N型的重掺杂半导体衬底中获得的具有高击穿电压的双极功率晶体管，其上叠加构成晶体管的集电极区的轻掺杂N型层。 晶体管具有包括重掺杂P型扩散的基极区，其从顶表面延伸到轻掺杂的N型层中。 晶体管还包括由在所述重掺杂P型扩散内的顶表面延伸的重掺杂N型扩散构成的发射极区域。 在深掺杂的P型扩散中获得重掺杂的P型扩散，该扩散从所述顶表面延伸到轻掺杂的N型层中，并由铝原子的受主杂质形成。

公开(公告)号：US5933734A

公开(公告)日：1999-08-03

申请号：US813009

申请日：1997-03-04

申请人： Giuseppe Ferla ,  Ferruccio Frisina

发明人： Giuseppe Ferla ,  Ferruccio Frisina

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L21/8236

CPC分类号： H01L29/7802 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/4238 ,  H01L2924/0002

摘要： A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the insulated gate layer is lowered.

摘要翻译： 高速MOS技术功率器件集成结构包括形成在第一导电类型的轻掺杂半导体层中的多个基本功能单元，所述基本功能单元包括由导电绝缘栅层覆盖的第二导电类型的沟道区 包括多晶硅层; 导电绝缘栅极层还包括叠加在多晶硅层上的高导电层，并且具有比多晶硅层的电阻率低得多的电阻率，使得由多晶硅层引入的电阻被由高导电层引入的电阻分流 并且绝缘栅极层的整体电阻率降低。