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    Integrated electronic device with edge-termination structure and manufacturing method thereof
    1.
    发明授权
    Integrated electronic device with edge-termination structure and manufacturing method thereof 有权
    具有边缘终端结构的集成电子装置及其制造方法

    公开(公告)号：US09018635B2

    公开(公告)日：2015-04-28

    申请号：US13221778

    申请日：2011-08-30

    申请人： Ferruccio Frisina ,  Angelo Magri' ,  Mario Giuseppe Saggio

    发明人： Ferruccio Frisina ,  Angelo Magri' ,  Mario Giuseppe Saggio

    IPC分类号： H01L29/16 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

    CPC分类号： H01L29/66666 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/402 ,  H01L29/66431 ,  H01L29/7811 ,  H01L29/7813

    摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

    摘要翻译： 一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

    Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device
    3.
    发明授权
    Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
    用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构

    公开(公告)号：US08039898B2

    公开(公告)日：2011-10-18

    申请号：US11824169

    申请日：2007-06-28

    申请人： Mario Giuseppe Saggio ,  Domenico Murabito ,  Ferruccio Frisina

    发明人： Mario Giuseppe Saggio ,  Domenico Murabito ,  Ferruccio Frisina

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

    摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically coupled to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.

    摘要翻译： 制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。 边缘终端结构由以下部分形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电耦合到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。 该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

    Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices
    4.
    发明授权
    Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices 有权
    用于制造集成在半导体衬底中的电子器件和相应器件的方法

    公开(公告)号：US07871880B2

    公开(公告)日：2011-01-18

    申请号：US11971155

    申请日：2008-01-08

    申请人： Ferruccio Frisina ,  Mario Giuseppe Saggio

    发明人： Ferruccio Frisina ,  Mario Giuseppe Saggio

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/44 ,  H01L21/28

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

    摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.

    摘要翻译： 一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区 ，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入 一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的注入源区域，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理 的身体和来源地区。

    PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE
    6.
    发明申请
    PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE 有权
    用于制造集成在半导体衬底和相应器件中的多电子电力器件的制造方法

    公开(公告)号：US20080224204A1

    公开(公告)日：2008-09-18

    申请号：US11971163

    申请日：2008-01-08

    申请人： Mario Giuseppe Saggio ,  Ferruccio Frisina ,  Simone Rascuna

    发明人： Mario Giuseppe Saggio ,  Ferruccio Frisina ,  Simone Rascuna

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

    摘要： A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by means of a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by means of a second implant step with a second implant dose, forming a surface semiconductor layer wherein body regions of the second type of conductivity are formed being aligned with the first sub-regions, carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region being aligned and in electric contact with the body regions.

    摘要翻译： 一种工艺制造集成在第一导电类型的半导体衬底上的多漏功率电子器件，其中形成漏极半导体层。 该方法包括：在半导体衬底上形成第一类电导率的第一半导体外延层，其形成第一导电类型的第一电阻率，形成第二类型的导电性的第一子区域，借助于第一选择性注入 以第一注入剂量进行步骤，借助于具有第二注入剂量的第二注入步骤形成第一类型导电性的第二子区域，形成表面半导体层，其中形成第二导电类型的主体区域与 所述第一子区域进行热扩散处理，使得所述第一子区域形成与所述身体区域对准并电接触的单个电连续列区域。

    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES
    7.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 有权
    用于制造集成在半导体衬底和相应器件中的电子器件的方法

    公开(公告)号：US20080185594A1

    公开(公告)日：2008-08-07

    申请号：US11971155

    申请日：2008-01-08

    申请人： Ferruccio Frisina ,  Mario Giuseppe Saggio

    发明人： Ferruccio Frisina ,  Mario Giuseppe Saggio

    IPC分类号： H01L29/24 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

    摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.

    摘要翻译： 一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区 ，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入 一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的注入源区域，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理 的身体和来源地区。