公开(公告)号：US07440256B2

公开(公告)日：2008-10-21

申请号：US10541494

申请日：2004-09-27

申请人： Masanori Hongo ,  Hiroyuki Nishikiori ,  Natsuyo Nagano ,  Takashi Ogura

发明人： Masanori Hongo ,  Hiroyuki Nishikiori ,  Natsuyo Nagano ,  Takashi Ogura

IPC分类号： H01G2/20 ,  H01G4/228

CPC分类号： H01L23/49805 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0919 ,  Y10T29/4913 ,  Y10T428/24777 ,  Y10T428/24926 ,  H01L2924/00014

摘要： A laminated ceramic substrate includes a side electrode in which a side edge electrode layer formed on a side edge portion of a ceramic layer overlaps with and connects to a side edge electrode layer formed on a side edge portion of another ceramic layer directly above and/or directly below the former ceramic layer. The side edge electrode layer includes a parallel wall unexposed and approximately parallel to a side surface of the laminated ceramic substrate and a perpendicular wall approximately perpendicular to the side surface of the laminated ceramic substrate. A length La of the parallel wall and a depth Lb of the parallel wall from the side surface of the laminated ceramic substrate have a relationship of La>Lb.

摘要翻译： 层叠陶瓷基板包括侧面电极，其中形成在陶瓷层的侧边缘部分上的侧边缘电极层与形成在另一陶瓷层的侧边缘部分上的侧边缘电极层重叠并连接到另一陶瓷层的正上方和/或 直接在以前的陶瓷层下面。 侧边电极层包括未曝光并且大致平行于层叠陶瓷基板的侧表面的平行壁和大致垂直于层叠陶瓷基板的侧表面的垂直壁。 平行壁的长度La和层叠陶瓷基板的侧面的平行壁的深度Lb具有La> Lb的关系。

公开(公告)号：US06565956B2

公开(公告)日：2003-05-20

申请号：US09994765

申请日：2001-11-28

申请人： Takashi Ogura ,  Shigehiro Horimoto ,  Masanori Hongo

发明人： Takashi Ogura ,  Shigehiro Horimoto ,  Masanori Hongo

IPC分类号： B32B300

CPC分类号： H01L23/49894 ,  B32B18/00 ,  C04B35/63416 ,  C04B2235/786 ,  C04B2237/04 ,  C04B2237/32 ,  C04B2237/68 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/24926 ,  H01L2924/00

摘要： A multilayer ceramic wiring board prepared from a plurality of sheets formed from a ceramic-incorporating material containing a ceramic powder and a binder resin and each having a pattern of one or a plurality of circuit elements printed on a surface thereof with use of a conductive mixture material containing an electrically conductive powder and a binder resin, by placing the sheets over one another to form a laminate, and compressing and firing the laminate. The mean particle size Rs of the ceramic powder is not greater than the value of (Rd−&sgr;d) wherein Rd is the mean particle size of the conductive powder, and &sgr;d is the standard deviation obtained when the distribution of the particle sizes of the conductive powder is expressed by a normal distribution function. This feature prevents formation of projections which would otherwise extend from the surface of one circuit element toward another circuit element when the elements are formed by firing the laminate.

公开(公告)号：US09939494B2

公开(公告)日：2018-04-10

申请号：US14400960

申请日：2012-05-15

申请人： Takashi Ogura

发明人： Takashi Ogura

IPC分类号： H02J7/00 ,  G01R31/36 ,  H01M10/48

CPC分类号： G01R31/3627 ,  G01R31/3648 ,  H01M10/48 ,  H01M2220/20

摘要： A concentration distribution in an active material of a battery unit is calculated by using a diffusion equation, and a first polarization elimination time taken for the concentration distribution in the active material to fall within an allowable range is calculated assuming that charge and discharge of the battery unit is not performed. A concentration distribution in an electrolyte of the battery unit is calculated by using a diffusion equation, and a second polarization elimination time taken for the concentration distribution in the electrolyte to fall within an allowable range is calculated assuming that the charge and the discharge of the battery unit is not performed. It is determined that polarization of the battery unit is eliminated when a time for which the charge and the discharge of the battery unit is not performed is longer than the longer one of the first polarization elimination time and the second polarization elimination time.

公开(公告)号：US09131292B2

公开(公告)日：2015-09-08

申请号：US13992653

申请日：2011-12-09

申请人： Ken'ichi Ejima ,  Takashi Ogura ,  Koji Moriguchi

发明人： Ken'ichi Ejima ,  Takashi Ogura ,  Koji Moriguchi

IPC分类号： H04R3/00 ,  H04L9/00 ,  H04R1/08

CPC分类号： H04R3/00 ,  H04L9/00 ,  H04L63/0428 ,  H04R1/08 ,  H04R2420/07 ,  H04W12/02

摘要： Provided is a wireless microphone system comprising a microphone and a wireless receiver, wherein the wireless microphone system is provided with: a normal communication mode in which communication is performed by using a normal unique word (UWN) preset in both the microphone and the wireless receiver devices; a confidential setting mode in which a confidential unique word (UWX) is transmitted without being set in either of said devices; and a confidential communication mode in which communication is performed by both said devices by using the confidential unique word (UWX) set by the confidential setting mode.

摘要翻译： 提供了一种包括麦克风和无线接收器的无线麦克风系统，其中无线麦克风系统被提供有：正常通信模式，其中通过使用在麦克风和无线接收机中预设的普通唯一字（UWN）来执行通信 设备; 保密设置模式，其中在不在所述设备中的任一个中发送机密唯一字（UWX）; 以及通过使用通过机密设置模式设置的机密唯一字（UWX）由两个所述设备进行通信的机密通信模式。

公开(公告)号：US08455925B2

公开(公告)日：2013-06-04

申请号：US13024004

申请日：2011-02-09

申请人： Masashige Moritoki ,  Takamasa Itou ,  Takashi Ogura ,  Tsutomu Himukai ,  Shigeaki Shimizu

发明人： Masashige Moritoki ,  Takamasa Itou ,  Takashi Ogura ,  Tsutomu Himukai ,  Shigeaki Shimizu

IPC分类号： H01L23/52

CPC分类号： H01L21/76895 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.

摘要翻译： 为了提供一种在抑制逻辑电路的接触电阻的增加的同时最大限度地实现存储电路的电容器电容的增加的半导体器件的结构及其制造方法。 当将具有构成逻辑电路区域的布线的局部互连层的层数指定为M并且指定具有构成存储器电路的布线的局部互连层的层数为N（M和N为自然数 并且满足M> N），在由（MN）层或（M-N + 1）层组成的互连层上提供电容元件。

公开(公告)号：US20120314837A1

公开(公告)日：2012-12-13

申请号：US13469792

申请日：2012-05-11

申请人： Osamu Tsujii ,  Noriaki Oguri ,  Takashi Ogura

发明人： Osamu Tsujii ,  Noriaki Oguri ,  Takashi Ogura

IPC分类号： H01J35/08 ,  G01N23/04

CPC分类号： H01J35/18 ,  H01J35/08 ,  H01J2235/081 ,  H01J2235/087 ,  H01J2235/183

摘要： A radiation transmission type target to be used for a radiation tube has a target metal 12 placed on a substrate 13, and has an antistatic member 14 placed on a surface of the substrate 13 opposite to a surface on which the target metal 12 is placed. The target suppresses its electrostatic charge, and enables the radiation tube to stable operate.

摘要翻译： 用于辐射管的辐射透射型靶具有放置在基板13上的目标金属12，并且具有放置在基板13的与放置目标金属12的表面相反的表面上的抗静电部件14。 目标抑制其静电电荷，使辐射管稳定运行。

公开(公告)号：US08108408B2

公开(公告)日：2012-01-31

申请号：US12521891

申请日：2008-06-12

申请人： Satoshi Kondo ,  Aki Yoneda ,  Ko Mizuno ,  Takashi Ogura

发明人： Satoshi Kondo ,  Aki Yoneda ,  Ko Mizuno ,  Takashi Ogura

IPC分类号： G06F7/00

CPC分类号： G06F17/30256 ,  G06K9/00684

摘要： An image recognition device includes: an image input unit obtaining an input image corresponding to a target image to be recognized; a similar image search unit searching out at least one similar image similar to the target image obtained by the image input unit from among images generated independently of the image recognition device, and unintentionally obtained; a keyword extraction unit extracting a plurality of keywords corresponding to candidates for a recognition result of the target image; a keyword analysis unit determining at least one likely keyword likely to be the recognition result of the target image from among the plurality of keywords extracted by the keyword extraction unit by analyzing the plurality of keywords; and a presentation unit outputting at least one likely keyword determined by the keyword analysis unit, as the recognition result of the target image.

摘要翻译： 图像识别装置包括：图像输入单元，获得与要识别的目标图像相对应的输入图像; 类似的图像搜索单元，从独立于图像识别装置生成的图像中搜索类似于由图像输入单元获得的目标图像的至少一个类似图像，并且无意地获得; 关键词提取单元，提取与所述目标图像的识别结果的候选对应的多个关键字; 关键字分析单元，通过分析所述多个关键字，从所述关键词提取单元提取的所述多个关键字中确定可能是所述目标图像的识别结果的至少一个可能关键字; 以及表示单元，输出由关键词分析单元确定的至少一个可能关键字作为目标图像的识别结果。

公开(公告)号：US20110152691A1

公开(公告)日：2011-06-23

申请号：US13060704

申请日：2010-06-04

申请人： Masako Ikeda ,  Takashi Ogura

发明人： Masako Ikeda ,  Takashi Ogura

IPC分类号： A61B8/14 ,  B29C39/12 ,  B29C47/00

CPC分类号： B06B1/0677 ,  A61B8/00 ,  A61B8/4405 ,  A61B8/4455 ,  G01N29/0672 ,  G10K11/002

摘要： An ultrasonic transducer includes: a piezoelectric transducer (1) emitting ultrasonic waves; and a backing layer (4) provided in contact with a back side of the piezoelectric transducer (1) and attenuating ultrasonic waves that are emitted toward the back side of the piezoelectric transducer (1) and have an opposite phase to the phase of ultrasonic waves emitted toward a front side of the piezoelectric transducer (1). The acoustic tubes (5) are disposed in the backing layer (4) such that a longitudinal direction of each acoustic tube (5) is in line with a traveling direction of the ultrasonic waves emitted by the piezoelectric transducer (1) toward the front and the back side. The acoustic tubes (5) have mutually different lengths on the basis of a principle of an acoustic wave synthesis, and attenuate in whole or in part the ultrasonic waves emitted by the piezoelectric transducer (1) toward the backing layer (4).

摘要翻译： 超声换能器包括：发射超声波的压电换能器（1） 以及设置成与所述压电换能器（1）的背面接触并且衰减朝向所述压电换能器（1）的背侧发射并且与超声波的相位相反的超声波的背衬层（4） 朝向压电换能器（1）的前侧发射。 声管（5）设置在背衬层（4）中，使得每个声管（5）的纵向方向与压电换能器（1）朝向前方发射的超声波的行进方向一致，以及 背面。 声管（5）基于声波合成的原理具有相互不同的长度，并且将压电换能器（1）发射的超声波全部或部分衰减到背衬层（4）。

公开(公告)号：US07947568B2

公开(公告)日：2011-05-24

申请号：US12548471

申请日：2009-08-27

申请人： Keiji Sakamoto ,  Takashi Ogura ,  Masashige Moritoki

发明人： Keiji Sakamoto ,  Takashi Ogura ,  Masashige Moritoki

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method of manufacturing a semiconductor device includes a process of forming a STI trench in a substrate, a process of forming a thermal oxide film on a sidewall and a bottom surface of the STI trench, a process of performing a plasma treatment on a surface of the thermal oxide film that is located at a bottom portion of the STI trench, and a process of forming an insulating film in the STI trench using a CVD method.

摘要翻译： 制造半导体器件的方法包括在衬底中形成STI沟槽的工艺，在STI沟槽的侧壁和底表面上形成热氧化膜的工艺，在表面上进行等离子体处理的工艺 位于STI沟槽的底部的热氧化膜，以及使用CVD法在STI沟槽中形成绝缘膜的工序。

公开(公告)号：US20080203500A1

公开(公告)日：2008-08-28

申请号：US12071126

申请日：2008-02-15

申请人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

发明人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.

摘要翻译： 一种设置有MIS型场效应晶体管的半导体器件，包括硅衬底，具有通过含硅绝缘膜形成在硅衬底上的高介电常数金属氧化物膜的栅极绝缘膜，含硅栅电极 形成在所述栅极绝缘膜上的侧壁，以及在所述栅电极的侧面上包含氧化硅作为构成材料的侧壁，其中，所述侧壁与所述栅电极的至少所述侧面之间插入有氮化硅膜。 该半导体器件尽管具有栅极长度小的精细结构，但能够实现低功耗和快速操作。