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    Semiconductor Device and Method for Fabricating Semiconductor Device
    11.
    发明申请
    Semiconductor Device and Method for Fabricating Semiconductor Device 有权
    用于制造半导体器件的半导体器件和方法

    公开(公告)号：US20080087957A1

    公开(公告)日：2008-04-17

    申请号：US11868051

    申请日：2007-10-05

    申请人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDOH ,  Masaru KITO

    发明人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDOH ,  Masaru KITO

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/1083 ,  H01L29/49 ,  H01L29/6659 ,  H01L29/7833

    摘要： According to an aspect of the present invention, there is provided a semiconductor device including a first conductive type semiconductor substrate, a gate electrode formed over the semiconductor substrate via a gate insulator, a first conductive impurity region buried in the semiconductor substrate, the first conductive impurity region being both sides of an extend plane, the extend plane being extended from side-walls of the gate electrode into the semiconductor substrate and a second conductive type source/drain region partially overlapping with the first conductive impurity region and extending from an end of the gate electrode at the semiconductor substrate to an outer region in the semiconductor substrate, wherein a first conductive impurity concentration at a prescribed depth in the overlapping portion between the first conductive impurity region and the source/drain region is lower than the first conductive impurity concentration in the first conductive impurity region except the overlapping portion corresponding to the prescribed depth.

    摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括第一导电型半导体衬底，通过栅绝缘体形成在半导体衬底上的栅电极，埋在半导体衬底中的第一导电杂质区，第一导电 杂质区域是延伸平面的两侧，所述延伸平面从所述栅电极的侧壁延伸到所述半导体衬底中，以及与所述第一导电杂质区域部分重叠并从所述第一导电杂质区域的一端延伸的第二导电型源极/ 半导体衬底上的栅极电极到半导体衬底中的外部区域，其中在第一导电杂质区域和源极/漏极区域之间的重叠部分中在规定深度处的第一导电杂质浓度低于第一导电杂质浓度 在除t外的第一导电杂质区 他的重叠部分对应于规定的深度。

    Semiconductor Device and Manufacturing Method Thereof
    12.
    发明申请
    Semiconductor Device and Manufacturing Method Thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US20080017922A1

    公开(公告)日：2008-01-24

    申请号：US11688449

    申请日：2007-03-20

    申请人： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH

    发明人： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L27/0605 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/12

    摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

    摘要翻译： 一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体 区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉 扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。

    Semiconductor Device and Manufacturing Method Thereof
    14.
    发明申请
    Semiconductor Device and Manufacturing Method Thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US20100295116A1

    公开(公告)日：2010-11-25

    申请号：US12850783

    申请日：2010-08-05

    申请人： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH

    发明人： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH

    IPC分类号： H01L29/792

    CPC分类号： H01L27/0605 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/12

    摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

    摘要翻译： 一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体 区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉 扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    15.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20100171162A1

    公开(公告)日：2010-07-08

    申请号：US12647836

    申请日：2009-12-28

    申请人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KITO ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Masaru KIDOH ,  Yoshiaki FUKUZUMI

    发明人： Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KITO ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Masaru KIDOH ,  Yoshiaki FUKUZUMI

    IPC分类号： H01L27/088 ,  H01L21/822

    CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

    摘要： Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.

    摘要翻译： 每个存储串包括：第一半导体层，具有在垂直方向上延伸到基板的一对柱状部分和形成为连接该一对柱状部分的下端的接合部分; 形成为包围第一半导体层的侧面的电荷蓄积层; 以及形成为围绕电荷蓄积层的侧表面的第一导电层。 柱状部分在垂直于垂直方向的第一方向上以第一间距排列，并且在垂直于垂直方向和第一方向的第二方向上以第二间距布置成交错图案。 第一导电层被配置为沿着第一方向以第一间距布置，并且沿着交错图案布置在第二方向上以波浪形的方式延伸。

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20100052042A1

    公开(公告)日：2010-03-04

    申请号：US12561451

    申请日：2009-09-17

    申请人： Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDO ,  Masaru KITO ,  Mitsuru SATO

    发明人： Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Masaru KIDO ,  Masaru KITO ,  Mitsuru SATO

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

    摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

    摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。