公开(公告)号：US20110284947A1

公开(公告)日：2011-11-24

申请号：US13198359

申请日：2011-08-04

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US20080315291A1

公开(公告)日：2008-12-25

申请号：US12140734

申请日：2008-06-17

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/00 ,  H01L21/31

CPC分类号： H01L27/105 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31645 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

摘要翻译： 非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。 存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体， 第一导体与第一块绝缘体相邻形成。

公开(公告)号：US20070290253A1

公开(公告)日：2007-12-20

申请号：US11765881

申请日：2007-06-20

申请人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US20130109157A1

公开(公告)日：2013-05-02

申请号：US13723601

申请日：2012-12-21

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US20120218821A1

公开(公告)日：2012-08-30

申请号：US13463889

申请日：2012-05-04

申请人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

发明人： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20120135593A1

公开(公告)日：2012-05-31

申请号：US13366509

申请日：2012-02-06

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20110012188A1

公开(公告)日：2011-01-20

申请号：US12728658

申请日：2010-03-22

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

IPC分类号： H01L27/105

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor memory device includes: a stacked body formed of a plurality of inter-layer insulating films and a plurality of electrode films alternately stacked and having a through-hole formed in the stacking direction; an electrode-side insulating film of a film thickness of 4 nm or more provided on an inner surface of the through-hole; a charge storage film provided on the electrode-side insulating film; a semiconductor-side insulating film of a film thickness of 4 nm or more provided on the charge storage film; and a semiconductor pillar buried in the through-hole.

摘要翻译： 半导体存储器件包括：由多个层间绝缘膜和交替层叠并具有沿堆叠方向形成的通孔的多个电极膜形成的层叠体; 设置在通孔的内表面上的膜厚度为4nm以上的电极侧绝缘膜; 设置在电极侧绝缘膜上的电荷存储膜; 设置在电荷存储膜上的膜厚度为4nm以上的半导体侧绝缘膜; 以及埋在通孔中的半导体柱。

公开(公告)号：US20100072538A1

公开(公告)日：2010-03-25

申请号：US12534576

申请日：2009-08-03

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20090090965A1

公开(公告)日：2009-04-09

申请号：US12244989

申请日：2008-10-03

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的存储器柱状半导体; 与记录柱状半导体接触的隧道绝缘层; 与隧道绝缘层接触并积累电荷的电荷累积层; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个存储器导电层。 电荷累积层的下部被隧道绝缘层和块绝缘层覆盖。

公开(公告)号：US20110002172A1

公开(公告)日：2011-01-06

申请号：US12728694

申请日：2010-03-22

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/02 ,  G11C11/34

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3413 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在存储层和电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在比第一电位低的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为高于第四电位 比第三个潜力。