公开(公告)号：US20110253672A1

公开(公告)日：2011-10-20

申请号：US12855206

申请日：2010-08-12

申请人： Masami Kamibayashi ,  Masahito Mori ,  Hiroyuki Kobayashi ,  Keizo Suzuki ,  Naoyuki Kofuji

发明人： Masami Kamibayashi ,  Masahito Mori ,  Hiroyuki Kobayashi ,  Keizo Suzuki ,  Naoyuki Kofuji

IPC分类号： C23F1/12 ,  H01L21/306 ,  C23F1/08

CPC分类号： H01J37/32678 ,  H01J37/32091 ,  H01L21/32136

摘要： The present invention is intended to improve the uniformity in a distribution function of incident ion energy inside a wafer surface, and realize uniform plasma processing (etching or the like) inside the wafer surface. In a plasma processing apparatus, a bias application portion of a placement electrode on which a wafer is placed is divided into an inner electrode and an outer electrode at positions near the center of the wafer and the edge thereof. Each of a first bias power and a second bias power to be used to accelerate ions incident on the wafer is bifurcated, and the resultant bias powers are fed to the inner electrode and outer electrode using a power distributor by adjusting the power ratio.

摘要翻译： 本发明旨在提高晶片表面内的入射离子能的分布函数的均匀性，并且在晶片表面内实现均匀的等离子体处理（蚀刻等）。 在等离子体处理装置中，放置晶片的放置电极的偏置施加部分在晶片的中心和边缘附近的位置被分成内电极和外电极。 用于加速入射在晶片上的离子的第一偏置功率和第二偏置功率分别被分叉，并且通过调节功率比，使用功率分配器将所得到的偏置功率馈送到内部电极和外部电极。

公开(公告)号：US20060076315A1

公开(公告)日：2006-04-13

申请号：US11242905

申请日：2005-10-05

申请人： Naoyuki Kofuji

发明人： Naoyuki Kofuji

IPC分类号： G01L21/30 ,  C23F1/00

CPC分类号： H01J37/32963 ,  H01J37/32935 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer.

公开(公告)号：US20050227470A1

公开(公告)日：2005-10-13

申请号：US11099609

申请日：2005-04-06

申请人： Naoyuki Kofuji

发明人： Naoyuki Kofuji

IPC分类号： H01L21/3065 ,  C23F4/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/02071 ,  H01L21/28061 ,  H01L21/32136 ,  H01L29/4941

摘要： A method for manufacturing a semiconductor device includes the steps of consecutively depositing a Poly-Si layer, a WN layer and a W layer on a SiO2 layer, forming a mask pattern on the W layer, selectively etching the W layer by using plasma in a first etching gas having a high etch selectivity ratio between W and WN, selectively etching the WN layer and the Poly-Si layer by using plasma in a second etching gas having a high etch selectivity between WN and Si, and selectively etching the Poly-Si layer 13 by using plasma in a third etching gas having a high etch selectivity between Si and silicon oxide.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在SiO 2层上连续沉积多晶硅层，WN层和W层，在W层上形成掩模图案，选择性蚀刻 通过在W和WN之间具有高蚀刻选择性比的第一蚀刻气体中使用等离子体，通过在WN和Si之间具有高蚀刻选择性的第二蚀刻气体中使用等离子体来选择性地蚀刻WN层和多晶硅层 并且通过在Si和氧化硅之间具有高蚀刻选择性的第三蚀刻气体中使用等离子体来选择性地蚀刻多晶硅层13。

公开(公告)号：US06784109B2

公开(公告)日：2004-08-31

申请号：US09920834

申请日：2001-08-03

申请人： Naoyuki Kofuji ,  Masaru Izawa

发明人： Naoyuki Kofuji ,  Masaru Izawa

IPC分类号： H01L21302

CPC分类号： H01L21/76838 ,  H01J37/3266 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76811 ,  H01L21/76814

摘要： Semiconductor devices having a wiring construction consisting of a conductive layer (a copper layer) and an insulating layer (a porous insulator layer with low dielectric constant) are fabricated. A method for forming wiring of semiconductor devices includes a first step for forming a first insulating material layer on a sample; a second step for forming a second insulating material layer with a dielectric constant less than 2.5; a third step for patterning the second insulating material layer by a plasma etching method; a fourth step for depositing a metal film on the second insulating material layer by a sputtering method; a fifth step for forming a copper layer on the metal film; and a sixth step for removing an unnecessary portion of the copper layer by Chemical Mechanical Polishing, wherein all the processes from the third to the fourth step are performed under process conditions.

摘要翻译： 制造具有由导电层（铜层）和绝缘层（具有低介电常数的多孔绝缘体层）组成的布线结构的半导体器件。 一种用于形成半导体器件布线的方法包括：在样品上形成第一绝缘材料层的第一步骤; 用于形成介电常数小于2.5的第二绝缘材料层的第二步骤; 通过等离子体蚀刻方法对第二绝缘材料层进行图案化的第三步骤; 通过溅射法在第二绝缘材料层上沉积金属膜的第四步骤; 在金属膜上形成铜层的第五步骤; 以及通过化学机械抛光除去铜层的不需要部分的第六步骤，其中在工艺条件下进行从第三步骤到第四步骤的所有处理。

公开(公告)号：US08093529B2

公开(公告)日：2012-01-10

申请号：US12194019

申请日：2008-08-19

申请人： Naoyuki Kofuji ,  Tsunehiko Tsubone

发明人： Naoyuki Kofuji ,  Tsunehiko Tsubone

IPC分类号： B23K10/00

CPC分类号： G01K13/00 ,  H01L21/67109 ,  H01L21/67248

摘要： A method of stably controlling the temperature of a sample placed on a sample stage to a desired temperature by estimating a sample temperature accurately, the sample stage including a refrigerant flow path to cool the sample stage, a heater to heat the sample stage, and a temperature sensor to measure the temperature of the sample stage. This method comprises the steps of: measuring in advance the variation-with-time of supply electric power to the heater, temperature of the sample, and temperature of the temperature sensor, without plasma processing; approximating the relation among the measured values using a simultaneous linear differential equation; estimating a sample temperature from the variation-with-time of sensor temperature y1, heater electric power u1, and plasma heat input by means of the Luenberger's states observer based on the simultaneous linear differential equation used for the approximation; and performing a feedback control of sample temperature using the estimated sample temperature.

摘要翻译： 通过精确地估计样品温度来稳定地将放置在样品台上的样品的温度控制到所需温度的方法，所述样品台包括用于冷却样品台的制冷剂流动路径，加热样品台的加热器和 温度传感器来测量样品台的温度。 该方法包括以下步骤：在不进行等离子体处理的情况下，预先测量供给电力与加热器的时间的变化，样品的温度和温度传感器的温度; 使用同时线性微分方程逼近测量值之间的关系; 基于用于近似的同时线性微分方程，通过Luenberger状态观测器从传感器温度y1，加热器电力u1和等离子体热输入的变化估计样本温度; 并使用估计的样品温度执行样品温度的反馈控制。

公开(公告)号：US20100167426A1

公开(公告)日：2010-07-01

申请号：US12723443

申请日：2010-03-12

申请人： Naoyuki Kofuji ,  Hiroshi Akiyama ,  Kouhei Satou

发明人： Naoyuki Kofuji ,  Hiroshi Akiyama ,  Kouhei Satou

IPC分类号： H01L21/66 ,  H01L21/3065

CPC分类号： H01L21/32136 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137

摘要： The invention provides a method for overcoming the drawbacks of deteriorated throughput, deteriorated reproducibility and plasma discharge instability when continuous discharge is performed during multiple steps of plasma etching. The present invention provides a gas switching method for switching from gas supply source 101 to gas supply source 111, wherein the gas supply source 101 is switched to gas supply source 111 by opening a valve 114 in advance, setting a flow rate of MFC 112 to a flow rate used in the subsequent step, letting the gas supply source 111 to flow toward an exhaust means 5, and closing the valve 114 simultaneously when opening the valve 113, wherein a volume V1 of an area of a gas pipe 115 surrounded by the valve 113, the valve 114 and the MFC 112 is set sufficiently smaller than a volume Vo from the shower plate to the valve 113 including a gas reservoir 10 and a processing gas line 8. The present arrangement enables to prevent the occurrence of pressure undershoot and to solve the problem of discharge instability.

摘要翻译： 本发明提供了一种在等离子体蚀刻的多个步骤中进行连续放电时，克服了劣化生产量，再现性劣化和等离子体放电不稳定性的缺陷的方法。 本发明提供一种从气体供给源101切换到气体供给源111的气体切换方法，其中，气体供给源101通过预先打开阀114而切换到气体供给源111，将MFC112的流量设定为 在后续步骤中使用的流量，使得气体供应源111朝向排气装置5流动，并且在打开阀113时同时关闭阀114，其中由管道115包围的气体管道115的区域的体积V1 阀113，阀114和MFC112被设定为足够小于从喷淋板到包括气体储存器10和处理气体管线8的阀113的体积Vo。本配置能够防止压力下冲的发生， 解决放电不稳定的问题。

公开(公告)号：US20080078505A1

公开(公告)日：2008-04-03

申请号：US11670048

申请日：2007-02-01

申请人： Naoyuki Kofuji ,  Hiroshi Akiyama ,  Kouhei Satou

发明人： Naoyuki Kofuji ,  Hiroshi Akiyama ,  Kouhei Satou

IPC分类号： H01L21/306

CPC分类号： H01L21/32136 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137

摘要： The invention provides a method for overcoming the drawbacks of deteriorated throughput, deteriorated reproducibility and plasma discharge instability when continuous discharge is performed during multiple steps of plasma etching. The present invention provides a gas switching method for switching from gas supply source 101 to gas supply source 111, wherein the gas supply source 101 is switched to gas supply source 111 by opening a valve 114 in advance, setting a flow rate of MFC 112 to a flow rate used in the subsequent step, letting the gas supply source 111 to flow toward an exhaust means 5, and closing the valve 114 simultaneously when opening the valve 113, wherein a volume V1 of an area of a gas pipe 115 surrounded by the valve 113, the valve 114 and the MFC 112 is set sufficiently smaller than a volume Vo from the shower plate to the valve 113 including a gas reservoir 10 and a processing gas line 8. The present arrangement enables to prevent the occurrence of pressure undershoot and to solve the problem of discharge instability.

摘要翻译： 本发明提供了一种在等离子体蚀刻的多个步骤中进行连续放电时，克服了劣化生产量，再现性劣化和等离子体放电不稳定性的缺陷的方法。 本发明提供一种从气体供给源101切换到气体供给源111的气体切换方法，其中，气体供给源101通过预先打开阀114而切换到气体供给源111，将MFC112的流量设定为 在后续步骤中使用的流量，使得气体供应源111朝向排气装置5流动，并且在打开阀113时同时关闭阀门114，其中气体管道115的区域的体积V 1被 阀113，阀114和MFC112被设定为充分小于从喷淋板到包括气体储存器10和加工气体管线8的阀113的体积Vo。本发明能够防止压力下冲的发生 并解决放电不稳定的问题。

公开(公告)号：US06677244B2

公开(公告)日：2004-01-13

申请号：US10135516

申请日：2002-05-01

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

摘要翻译： 用于蚀刻具有栅极氧化膜的样品的等离子体处理方法包括使用电磁波在真空室中产生等离子体，向样品施加rf偏置功率，在样品的充电电压达到击穿之前关闭rf偏置功率 电压，在样品的充电电压基本上下降之后接通rf偏置功率，并且重复接通和关断rf偏置功率以处理样品。 关闭时间至少比准时更长。

公开(公告)号：US10310321B2

公开(公告)日：2019-06-04

申请号：US14404529

申请日：2012-06-21

申请人： Koji Hirata ,  Hiroyuki Minemura ,  Yumiko Anzai ,  Tetsuya Nishida ,  Jiro Yamamoto ,  Naoyuki Kofuji ,  Hidehiro Ikeda ,  Nobuyuki Kimura

发明人： Koji Hirata ,  Hiroyuki Minemura ,  Yumiko Anzai ,  Tetsuya Nishida ,  Jiro Yamamoto ,  Naoyuki Kofuji ,  Hidehiro Ikeda ,  Nobuyuki Kimura

IPC分类号： G02F1/1335 ,  G02B5/30 ,  G03B21/20 ,  G03B33/12 ,  H04N9/31 ,  G02F1/1333

摘要： In order to improve a characteristic of an optical element, an optical element (polarizing filter) including a substrate 1S having a wire-grid region 1A and a peripheral region 2A positioned on an outer periphery thereof is made to have the following configuration. A wire-grid in which a plurality of line-shaped wires P10 made of Al and extending in a y direction are arranged at spaces S in an x direction is provided in the wire-grid region 1A of the substrate 1S, and a pattern (repetitive pattern) in which a plurality of protruding portions P20 made of Al are arranged is provided in the peripheral region 2A. This pattern is, for example, a checkerboard pattern. According to the above-mentioned configuration, the plurality of wires P10 can be arranged so that their respective ends are spaced apart from an end of the substrate 1S, so that the wires P10 can be prevented from being deformed and nicked. Also, by the plurality of protruding portions P20 in the peripheral region 2A, it is possible to prevent water from entering the wire-grid region 1A.

公开(公告)号：US20150234230A1

公开(公告)日：2015-08-20

申请号：US14404529

申请日：2012-06-21

申请人： Koji Hirata ,  Hiroyuki Minemura ,  Yumiko Anzai ,  Tetsuya Nishida ,  Jiro Yamamoto ,  Naoyuki Kofuji ,  Hidehiro Ikeda ,  Nobuyuki Kimura

发明人： Koji Hirata ,  Hiroyuki Minemura ,  Yumiko Anzai ,  Tetsuya Nishida ,  Jiro Yamamoto ,  Naoyuki Kofuji ,  Hidehiro Ikeda ,  Nobuyuki Kimura

IPC分类号： G02F1/1335 ,  G02B5/30

CPC分类号： G02F1/133528 ,  G02B5/30 ,  G02B5/3058 ,  G02F2001/133548 ,  G03B21/2073 ,  G03B33/12 ,  H04N9/3105 ,  H04N9/3167

摘要： In order to improve a characteristic of an optical element, an optical element (polarizing filter) including a substrate 1S having a wire-grid region 1A and a peripheral region 2A positioned on an outer periphery thereof is made to have the following configuration. A wire-grid in which a plurality of line-shaped wires P10 made of Al and extending in a y direction are arranged at spaces S in an x direction is provided in the wire-grid region 1A of the substrate 1S, and a pattern (repetitive pattern) in which a plurality of protruding portions P20 made of Al are arranged is provided in the peripheral region 2A. This pattern is, for example, a checkerboard pattern. According to the above-mentioned configuration, the plurality of wires P10 can be arranged so that their respective ends are spaced apart from an end of the substrate 1S, so that the wires P10 can be prevented from being deformed and nicked. Also, by the plurality of protruding portions P20 in the peripheral region 2A, it is possible to prevent water from entering the wire-grid region 1A.

摘要翻译： 为了提高光学元件的特性，使具有线栅区域1A的基板1S和位于其外周的周边区域2A的光学元件（偏振滤光器）具有以下结构。 在基板1S的线栅区域1A中设置有线状，其中由Al构成的多条线状导线P10沿y方向布置在x方向的间隔S处，并且形成图案（重复 图案），其中布置有多个由Al制成的突出部分P20设置在周边区域2A中。 该模式例如是棋盘图案。 根据上述结构，可以将多根电线P10配置成使它们各自的端部与基板1S的一端分开，从而可以防止电线P10变形和断开。 此外，通过周边区域2A中的多个突出部P20，可以防止水进入线栅区域1A。