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    NAND MEMORY MANAGEMENT
    12.
    发明申请
    NAND MEMORY MANAGEMENT 有权
    NAND记忆管理

    公开(公告)号：US20140115231A1

    公开(公告)日：2014-04-24

    申请号：US13658449

    申请日：2012-10-23

    申请人： Ravi H. Motwani ,  Pranav Kalavade

    发明人： Ravi H. Motwani ,  Pranav Kalavade

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F11/1072 ,  G06F12/02

    摘要： Apparatus, systems, and methods manage NAND memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述管理NAND存储器的装置，系统和方法。 在一个实施例中，一种装置包括存储器控制器逻辑，用于将二进制奇偶校验码应用于二进制串并将二进制串转换为三进制串。 还公开并要求保护其他实施例。

    Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse
    14.
    发明授权
    Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse 有权
    通过反向场脉冲在浮动栅极存储器件中的充电平衡加速度

    公开(公告)号：US08542531B2

    公开(公告)日：2013-09-24

    申请号：US12829729

    申请日：2010-07-02

    申请人： Nathan R. Franklin ,  Pranav Kalavade

    发明人： Nathan R. Franklin ,  Pranav Kalavade

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3454 ,  G11C11/10 ,  G11C11/5642

    摘要： Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

    摘要翻译： 公开了使用浮动栅极存储器单元在非易失性存储器件中加速电荷平衡的方法。 还公开了使用充电平衡加速度的存储器件和存储系统。 在一种这样的方法中，将编程脉冲施加到字线以改变存储在正被编程的存储器单元的浮动栅极上的电荷量。 然后仅使用大于或等于约0伏的电压将反向场脉冲施加到存储器单元。 反向场脉冲通过将捕获在绝缘氧化物层中的任何电子移动到稳定位置来加速电荷平衡，使得阈值电压稳定。 在反向场脉冲之后，执行程序验证操作，并且根据需要施加附加的编程脉冲和反向场脉冲以正确编程存储单元。

    NAND PRE-READ ERROR RECOVERY
    17.
    发明申请
    NAND PRE-READ ERROR RECOVERY 有权
    NAND预读错误恢复

    公开(公告)号：US20150378815A1

    公开(公告)日：2015-12-31

    申请号：US14314663

    申请日：2014-06-25

    申请人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

    发明人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2029/0411

    摘要： Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method may include applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method may further include determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.

    摘要翻译： 公开并描述了用于对NAND存储器件中的存储器页进行编程的技术。 在一个示例中，方法可以包括应用用于页面的较低页面编程和下部页面的预读数据的初始编程脉冲。 该方法还可以包括确定是否对下部页面的数据应用错误恢复操作。 存储表示用于编程上页数据的辅助编程脉冲的数据，并且基于次要编程脉冲和下部页面的数据对高位页数据进行编程。

    METHOD, APPARATUS AND SYSTEM FOR DETERMINING ACCESS TO A MEMORY ARRAY
    18.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR DETERMINING ACCESS TO A MEMORY ARRAY 审中-公开
    用于确定访问存储阵列的方法，装置和系统

    公开(公告)号：US20130339603A1

    公开(公告)日：2013-12-19

    申请号：US13997514

    申请日：2011-12-23

    申请人： Feng Zhu ,  Pranav Kalavade ,  Iwen Chao

    发明人： Feng Zhu ,  Pranav Kalavade ,  Iwen Chao

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0688 ,  G06F3/0614 ,  G06F3/0638 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  G11C2211/5641 ,  G11C2211/5648

    摘要： Techniques and mechanisms for determining a sequence of accessed to a memory array. In an embodiment, a memory array includes multi-level cells and single-level cells interleaved with one another, where bits of the multi-level cells and single-level cells are variously allocated to different logical pages. In another embodiment, requests to access the memory array are ordered according to a sequence of page rounds to avoid an access event which includes a type of successive accessing of adjacent multi-level cells.

    摘要翻译： 用于确定访问存储器阵列的序列的技术和机制。 在一个实施例中，存储器阵列包括多级单元和彼此交错的单级单元，其中多级单元和单级单元的位被不同地分配给不同的逻辑页。 在另一个实施例中，访问存储器阵列的请求根据页面循环的顺序排序，以避免包括相邻多级单元的连续访问类型的访问事件。

    CHARGE EQUILIBRIUM ACCELERATION IN A FLOATING GATE MEMORY DEVICE VIA A REVERSE FIELD PULSE
    19.
    发明申请
    CHARGE EQUILIBRIUM ACCELERATION IN A FLOATING GATE MEMORY DEVICE VIA A REVERSE FIELD PULSE 有权
    通过反向场脉冲在浮动门存储器装置中的充电平衡加速

    公开(公告)号：US20120002482A1

    公开(公告)日：2012-01-05

    申请号：US12829729

    申请日：2010-07-02

    申请人： Nathan R. Franklin ,  Pranav Kalavade

    发明人： Nathan R. Franklin ,  Pranav Kalavade

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3454 ,  G11C11/10 ,  G11C11/5642

    摘要： Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

    摘要翻译： 公开了使用浮动栅极存储器单元在非易失性存储器件中加速电荷平衡的方法。 还公开了使用充电平衡加速度的存储器件和存储系统。 在一种这样的方法中，将编程脉冲施加到字线以改变存储在正被编程的存储器单元的浮动栅极上的电荷量。 然后仅使用大于或等于约0伏的电压将反向场脉冲施加到存储器单元。 反向场脉冲通过将捕获在绝缘氧化物层中的任何电子移动到稳定位置来加速电荷平衡，使得阈值电压稳定。 在反向场脉冲之后，执行程序验证操作，并且根据需要施加附加的编程脉冲和反向场脉冲以正确编程存储单元。

    DRAIN SELECT GATE VOLTAGE MANAGEMENT
    20.
    发明申请
    DRAIN SELECT GATE VOLTAGE MANAGEMENT 有权
    排水门电压管理

    公开(公告)号：US20110216600A1

    公开(公告)日：2011-09-08

    申请号：US12715530

    申请日：2010-03-02

    申请人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    发明人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/0433

    摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。