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    Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse
    2.
    发明授权
    Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse 有权
    通过反向场脉冲在浮动栅极存储器件中的充电平衡加速度

    公开(公告)号：US08542531B2

    公开(公告)日：2013-09-24

    申请号：US12829729

    申请日：2010-07-02

    申请人： Nathan R. Franklin ,  Pranav Kalavade

    发明人： Nathan R. Franklin ,  Pranav Kalavade

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3454 ,  G11C11/10 ,  G11C11/5642

    摘要： Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

    摘要翻译： 公开了使用浮动栅极存储器单元在非易失性存储器件中加速电荷平衡的方法。 还公开了使用充电平衡加速度的存储器件和存储系统。 在一种这样的方法中，将编程脉冲施加到字线以改变存储在正被编程的存储器单元的浮动栅极上的电荷量。 然后仅使用大于或等于约0伏的电压将反向场脉冲施加到存储器单元。 反向场脉冲通过将捕获在绝缘氧化物层中的任何电子移动到稳定位置来加速电荷平衡，使得阈值电压稳定。 在反向场脉冲之后，执行程序验证操作，并且根据需要施加附加的编程脉冲和反向场脉冲以正确编程存储单元。

    CHARGE EQUILIBRIUM ACCELERATION IN A FLOATING GATE MEMORY DEVICE VIA A REVERSE FIELD PULSE
    3.
    发明申请
    CHARGE EQUILIBRIUM ACCELERATION IN A FLOATING GATE MEMORY DEVICE VIA A REVERSE FIELD PULSE 有权
    通过反向场脉冲在浮动门存储器装置中的充电平衡加速

    公开(公告)号：US20120002482A1

    公开(公告)日：2012-01-05

    申请号：US12829729

    申请日：2010-07-02

    申请人： Nathan R. Franklin ,  Pranav Kalavade

    发明人： Nathan R. Franklin ,  Pranav Kalavade

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3454 ,  G11C11/10 ,  G11C11/5642

    摘要： Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

    摘要翻译： 公开了使用浮动栅极存储器单元在非易失性存储器件中加速电荷平衡的方法。 还公开了使用充电平衡加速度的存储器件和存储系统。 在一种这样的方法中，将编程脉冲施加到字线以改变存储在正被编程的存储器单元的浮动栅极上的电荷量。 然后仅使用大于或等于约0伏的电压将反向场脉冲施加到存储器单元。 反向场脉冲通过将捕获在绝缘氧化物层中的任何电子移动到稳定位置来加速电荷平衡，使得阈值电压稳定。 在反向场脉冲之后，执行程序验证操作，并且根据需要施加附加的编程脉冲和反向场脉冲以正确编程存储单元。

    PROGRAM VT SPREAD FOLDING FOR NAND FLASH MEMORY PROGRAMMING
    5.
    发明申请
    PROGRAM VT SPREAD FOLDING FOR NAND FLASH MEMORY PROGRAMMING 有权
    用于NAND闪存编程的程序VT SPREAD折叠

    公开(公告)号：US20150179267A1

    公开(公告)日：2015-06-25

    申请号：US14139219

    申请日：2013-12-23

    申请人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

    发明人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

    IPC分类号： G11C16/10 ,  G11C16/28

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

    摘要： Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

    摘要翻译： 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。

    Automatic selective slow program convergence
    6.
    发明授权
    Automatic selective slow program convergence 有权
    自动选择性慢程序融合

    公开(公告)号：US08411508B2

    公开(公告)日：2013-04-02

    申请号：US12573579

    申请日：2009-10-05

    申请人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

    发明人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

    IPC分类号： G11C11/34

    CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

    摘要翻译： 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。

    NAND MEMORY MANAGEMENT
    9.
    发明申请
    NAND MEMORY MANAGEMENT 有权
    NAND记忆管理

    公开(公告)号：US20140115231A1

    公开(公告)日：2014-04-24

    申请号：US13658449

    申请日：2012-10-23

    申请人： Ravi H. Motwani ,  Pranav Kalavade

    发明人： Ravi H. Motwani ,  Pranav Kalavade

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F11/1072 ,  G06F12/02

    摘要： Apparatus, systems, and methods manage NAND memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述管理NAND存储器的装置，系统和方法。 在一个实施例中，一种装置包括存储器控制器逻辑，用于将二进制奇偶校验码应用于二进制串并将二进制串转换为三进制串。 还公开并要求保护其他实施例。