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19 条记录 (耗时 0.027 秒)

    VCO TUNING WITH TEMPERATURE COMPENSATION
    11.
    发明申请
    VCO TUNING WITH TEMPERATURE COMPENSATION 审中-公开
    VCO调谐与温度补偿

    公开(公告)号：US20100225402A1

    公开(公告)日：2010-09-09

    申请号：US12400658

    申请日：2009-03-09

    申请人： Jeongsik Yang ,  Jin Wook Kim ,  Sang-Oh Lee

    发明人： Jeongsik Yang ,  Jin Wook Kim ,  Sang-Oh Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/099 ,  H03L1/022 ,  H03L7/10 ,  H03L7/113 ,  H03L2207/06

    摘要： Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described.

    摘要翻译： 在VCO的粗调模式下为压控振荡器（VCO）设置微调输入信号Vtune的技术。 在一个示例性实施例中，在微调模式期间，微调输入信号变得温度依赖于在微调模式期间Vtune随温度的可能变化。 进一步描述采用这些技术的方法和装置。

    System for I-Q phase mismatch detection and correction
    12.
    发明授权
    System for I-Q phase mismatch detection and correction 有权
    用于I-Q相位失配检测和校正的系统

    公开(公告)号：US08854098B2

    公开(公告)日：2014-10-07

    申请号：US13011716

    申请日：2011-01-21

    申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

    发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

    IPC分类号： H03H11/16 ,  H03D7/14 ,  H03D7/16 ,  H03L7/081 ,  H04L27/36 ,  H04L27/38

    CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

    摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

    摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

    Fast-switching low-noise charge pump
    13.
    发明授权
    Fast-switching low-noise charge pump 有权
    快速切换低噪声电荷泵

    公开(公告)号：US08552774B2

    公开(公告)日：2013-10-08

    申请号：US13208456

    申请日：2011-08-12

    申请人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    发明人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0896 ,  H03L7/18

    摘要： In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

    摘要翻译： 在本发明的一个实施例中，公开了一种用于电荷泵的方法。 该方法包括偏置多个晶体管; 切换一对主晶体管开关以通过偏置晶体管施加或去除输出端子上的净电荷; 并且当主晶体管开关断开时，接通辅助晶体管开关。 辅助晶体管开关导通时，为主晶体管开关和偏置晶体管之间的节点提供辅助均衡通路。 辅助均衡路径均衡中间节点之间的电压，以快速关闭偏置晶体管，并降低电荷泵输出端子上的噪声。

    Fast-switching low-noise charge pump
    14.
    发明授权
    Fast-switching low-noise charge pump 有权
    快速切换低噪声电荷泵

    公开(公告)号：US08018269B2

    公开(公告)日：2011-09-13

    申请号：US11953575

    申请日：2007-12-10

    申请人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    发明人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    IPC分类号： G05F1/10

    CPC分类号： H03L7/0896 ,  H03L7/18

    摘要： In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

    摘要翻译： 在本发明的一个实施例中，公开了一种用于电荷泵的方法。 该方法包括偏置多个晶体管; 切换一对主晶体管开关以通过偏置晶体管施加或去除输出端子上的净电荷; 并且当主晶体管开关断开时，接通辅助晶体管开关。 辅助晶体管开关导通时，为主晶体管开关和偏置晶体管之间的节点提供辅助均衡通路。 辅助均衡路径均衡中间节点之间的电压，以快速关闭偏置晶体管，并降低电荷泵输出端子上的噪声。

    Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
    18.
    发明授权
    Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle 失效
    即使两个信号之间的相位延迟大于一个周期，也可以使用单个正向和反向时钟信号导出通用同步时钟信号

    公开(公告)号：US06647506B1

    公开(公告)日：2003-11-11

    申请号：US09452274

    申请日：1999-11-30

    申请人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

    发明人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

    IPC分类号： G06F104

    CPC分类号： G06F1/10

    摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

    摘要翻译： 同步总线系统包括具有连接到多个设备中的每一个的正向时钟段和反向时钟段的时钟线。 正向时钟段承载正向时钟信号，反向时钟段承载反向时钟信号。 在每个设备中提供的同步时钟电路接收正向时钟信号和反向时钟信号。 使用接收到的时钟信号，同步时钟电路产生通用同步时钟信号，其在所有设备中是同步的。 提供在装置的至少一部分中的偏斜校正电路校正通用同步时钟信号与用于在设备之间传送数据的一个或多个数据信号之间的偏斜。

    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
    19.
    发明授权
    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream 失效
    用于半导体芯片的I / O接口的系统利用在第一数据流中向每个数据元素添加参考元素并解释以恢复第二数据流的数据元素

    公开(公告)号：US06477592B1

    公开(公告)日：2002-11-05

    申请号：US09369636

    申请日：1999-08-06

    申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    IPC分类号： G06F1320

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

    摘要： An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

    摘要翻译： I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。