公开(公告)号：US09118371B2

公开(公告)日：2015-08-25

申请号：US14281916

申请日：2014-05-20

Applicant: MEDIATEK INC.

Inventor： Chi-Hsueh Wang ,  Yang-Chuan Chen ,  Hsiang-Hui Chang ,  Li-Shin Lai ,  Khurram Muhammad

IPC: H04K1/02 ,  H04B1/04 ,  H04L25/08 ,  H03F3/217 ,  H03F3/24 ,  H03G3/00

CPC classification number: H04B1/0475 ,  H03F1/02 ,  H03F3/2178 ,  H03F3/24 ,  H03G3/002 ,  H04B2001/045 ,  H04L25/08

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract translation: 数字发射机包括：多个转换装置，被配置为根据多个数字输入信号产生多个转换信号; 补偿装置，被配置为根据所述多个数字输入信号生成至少一个补偿信号; 以及组合电路，被配置为根据所述多个转换信号和所述至少一个补偿信号输出放大的输出信号。

公开(公告)号：US20170272074A1

公开(公告)日：2017-09-21

申请号：US15611822

申请日：2017-06-02

Applicant: MediaTek Inc.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H03K19/0175 ,  H03F3/217 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L27/20 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/34 ,  H04L25/08

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US09425796B2

公开(公告)日：2016-08-23

申请号：US14272522

申请日：2014-05-08

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chih-Jung Chen ,  Hsiang-Hui Chang

IPC: H04L27/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.

Abstract translation: 数据转换装置包括：数据采样电路，被配置为对数字信号进行上采样以根据时钟信号产生上采样信号; 电压电平发生电路，被布置成产生可调电压; 以及信号转换电路，被配置为根据可调电压和上采样信号产生转换信号。

公开(公告)号：US20160149652A1

公开(公告)日：2016-05-26

申请号：US14923445

申请日：2015-10-27

Applicant: MEDIATEK INC.

Inventor： Yen-Lin Huang ,  Hsiang-Hui Chang ,  Hung-Tao Hsieh ,  Gary A. Anwyl ,  Thomas Edward Pare, JR.

IPC: H04B17/14 ,  H04L25/02 ,  H04B7/04 ,  H04B7/06

CPC classification number: H04B17/14 ,  H04B7/0413 ,  H04B7/0617 ,  H04L25/0202

Abstract: A method operative on a wireless transceiver device for performing beamforming calibration includes: measuring at least one joint signal response of at least one circuit loopback between a transmitter of the wireless transceiver device and a receiver of the wireless transceiver device to determine the measurement result; and calibrating joint signal path mismatch according to the measurement result for s multiple antenna beamforming system operating on the wireless transceiver device.

Abstract translation: 一种在用于执行波束成形校准的无线收发器设备上操作的方法包括：测量无线收发器设备的发射机与无线收发器设备的接收机之间的至少一个电路环回的至少一个联合信号响应，以确定测量结果; 并且根据在无线收发器设备上操作的多天线波束成形系统的测量结果来校准联合信号路径失配。

公开(公告)号：US09124267B2

公开(公告)日：2015-09-01

申请号：US14281902

申请日：2014-05-20

Applicant: MEDIATEK INC.

Inventor： Wen-Chieh Wang ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  I-Wen Liu ,  Khurram Muhammad ,  Chih-Ming Hung

IPC: H04L27/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract translation: 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。

公开(公告)号：US20140348279A1

公开(公告)日：2014-11-27

申请号：US14273547

申请日：2014-05-09

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract translation: 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US20140086360A1

公开(公告)日：2014-03-27

申请号：US14037329

申请日：2013-09-25

Applicant: MEDIATEK INC.

Inventor： Hsiang-Hui Chang ,  Li-Shin Lai ,  Chih-Jung Chen ,  Chih-Hao Sun

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H04B1/0483 ,  H04L27/04

Abstract: A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals.

Abstract translation: 发射机包括第一信道和第二信道。 第一通道包括第一混频器，用于处理第一输入信号以产生第一输出信号; 第二通道包括第二混频器，其中第二通道不接收任何输入信号。 当发射机在第一模式下操作时，第一混频器和第二混频器都接收振荡信号。

公开(公告)号：US20240186955A1

公开(公告)日：2024-06-06

申请号：US18525884

申请日：2023-12-01

Applicant: MEDIATEK INC.

Inventor： Chen-Yen Ho ,  Hsiang-Hui Chang ,  Ya-Ting Hsu ,  Ke-Horng Chen

IPC: H03F1/02

CPC classification number: H03F1/0216 ,  H03F3/21

Abstract: A digital envelope tracking (DET) supply modulator is provided. The DET supply modulator includes a switching converter, a dynamic switched-capacitor circuit and a digital control circuit. The switching converter converts an input supply voltage into an output envelope tracking (ET) voltage according to a first control signal. The dynamic switched-capacitor circuit outputs multiple supplement voltages for supplementing alternating current (AC) components of the output ET voltage by multiple stages. More particularly, the dynamic switched-capacitor circuit comprises multiple switched-capacitor cells and a selection circuit, wherein the selection circuit is coupled to the multiple switched-capacitor cells. In detail, the multiple switched-capacitor cells generate the multiple supplement voltages, respectively, and the selection circuit controls switching of each of the multiple switched-capacitor cells according to a second control signal. The digital control circuit generates the first control signal and the second control signal according to a target envelope waveform of the output ET voltage.

公开(公告)号：US09577638B2

公开(公告)日：2017-02-21

申请号：US14273547

申请日：2014-05-09

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract translation: 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US20160373243A1

公开(公告)日：2016-12-22

申请号：US15255159

申请日：2016-09-02

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract translation: 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。