公开(公告)号：US20190115646A1

公开(公告)日：2019-04-18

申请号：US16120446

申请日：2018-09-03

Applicant: MEDIATEK INC.

Inventor： Shih-Chia Chiu ,  Yen-Ju Lu ,  Wen-Chou Wu ,  Nan-Cheng Chen

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/31 ,  H01L23/14 ,  H01Q21/06

Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

公开(公告)号：US20190068300A1

公开(公告)日：2019-02-28

申请号：US16056549

申请日：2018-08-07

Applicant: MEDIATEK INC.

Inventor： Yen-Ju Lu ,  Chih-Ming Hung ,  Wen-Chou Wu ,  Nan-Cheng Chen

IPC: H04B17/16

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

公开(公告)号：US09158880B2

公开(公告)日：2015-10-13

申请号：US14043197

申请日：2013-10-01

Applicant: MediaTek Inc.

Inventor： Fu-Kang Pan ,  Nan-Cheng Chen ,  Shih-Chieh Lin ,  Hui-Chi Tang ,  Ying Liu ,  Yang Liu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Abstract translation: 提供了印刷电路板（PCB）的布局方法。 获得要安装在PCB上的动态随机存取存储器（DRAM）的存储器类型。 根据DRAM的存储器类型从数据库获得模块组，其中模块组包括多个路由模块。 获得多个PCB参数。 根据PCB参数从模块组中选择一个特定的路由模块。 具体的路由模块被实现为PCB的布局设计。 特定路由模块包括关于主芯片，存储芯片以及主芯片和存储芯片之间的路由配置的布局信息。

公开(公告)号：US20150097277A1

公开(公告)日：2015-04-09

申请号：US14045803

申请日：2013-10-04

Applicant: MEDIATEK INC.

Inventor： Nan-Cheng Chen ,  Che-Ya Chou

IPC: H01L23/498 ,  H01L25/07

CPC classification number: H01L25/18 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract translation: 系统级封装包括封装载体; 第一半导体管芯，其具有管芯面和管芯边缘，所述第一半导体管芯正面朝下地组装到所述封装载体的芯片侧，其中，多个接触焊盘位于所述管芯面上; 安装在所述封装载体上并与所述第一半导体管芯相邻的第二半导体管芯; 在所述第一半导体管芯和所述封装载体之间的再布线层压结构，所述重新布线层压结构包括重新布线的金属层，其中所述重新布线的金属层的至少一部分突出超过所述管芯边缘; 以及布置在重新布线层压结构上的多个铜柱凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US11373957B2

公开(公告)日：2022-06-28

申请号：US16994764

申请日：2020-08-17

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/14 ,  H01L23/00 ,  H01Q21/06

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20210036405A1

公开(公告)日：2021-02-04

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

公开(公告)号：US10128192B2

公开(公告)日：2018-11-13

申请号：US15498542

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Min-Chen Lin ,  Che-Ya Chou ,  Nan-Cheng Chen

IPC: H01L25/16 ,  H01L23/12 ,  H01L23/528 ,  H01L23/31 ,  H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

公开(公告)号：US09846756B2

公开(公告)日：2017-12-19

申请号：US14843113

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang Pan ,  Nan-Cheng Chen ,  Shih-Chieh Lin ,  Hui-Chi Tang ,  Ying Liu ,  Yang Liu ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

公开(公告)号：US20160005726A1

公开(公告)日：2016-01-07

申请号：US14850962

申请日：2015-09-11

Applicant: MEDIATEK INC.

Inventor： Nan-Cheng Chen ,  Che-Ya Chou

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract translation: 系统级封装包括封装载体; 第一半导体管芯，其具有管芯面和管芯边缘，所述第一半导体管芯正面朝下地组装到所述封装载体的芯片侧，其中，多个接触焊盘位于所述管芯面上; 安装在所述封装载体上并与所述第一半导体管芯相邻的第二半导体管芯; 在所述第一半导体管芯和所述封装载体之间的重新布线层压结构，所述重新布线层压结构包括重新布线的金属层，其中所述重新布线的金属层的至少一部分突出超过所述管芯边缘; 以及布置在重新布线层压结构上的多个铜柱凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US09165877B2

公开(公告)日：2015-10-20

申请号：US14045803

申请日：2013-10-04

Applicant: MEDIATEK INC.

Inventor： Nan-Cheng Chen ,  Che-Ya Chou

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract translation: 系统级封装包括封装载体; 第一半导体管芯，其具有管芯面和管芯边缘，所述第一半导体管芯正面朝下地组装到所述封装载体的芯片侧，其中，多个接触焊盘位于所述管芯面上; 安装在所述封装载体上并与所述第一半导体管芯相邻的第二半导体管芯; 在所述第一半导体管芯和所述封装载体之间的重新布线层压结构，所述重新布线层压结构包括重新布线的金属层，其中所述重新布线的金属层的至少一部分突出超过所述管芯边缘; 以及布置在重新布线层压结构上的多个铜柱凸块，用于将第一半导体管芯与封装载体电连接。