公开(公告)号：US20220352084A1

公开(公告)日：2022-11-03

申请号：US17748308

申请日：2022-05-19

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US10186488B2

公开(公告)日：2019-01-22

申请号：US15672440

申请日：2017-08-09

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/50

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

公开(公告)号：US09905515B2

公开(公告)日：2018-02-27

申请号：US14686783

申请日：2015-04-15

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Tao Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.

公开(公告)号：US09198281B2

公开(公告)日：2015-11-24

申请号：US14100444

申请日：2013-12-09

Applicant: MediaTek Inc.

Inventor： Tao Cheng

IPC: H05K1/02 ,  H01L23/495 ,  G06F17/50 ,  H01L23/64 ,  H01L23/00

CPC classification number: H05K1/025 ,  G06F17/5077 ,  H01L23/49541 ,  H01L23/64 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected from each other.

Abstract translation: 提供半导体封装的引线框架。 引线框架包括管芯焊盘，侧轨，连杆和多个引线。 侧轨位于管芯垫周围。 连接杆连接管芯焊盘和侧轨。 引线从侧轨延伸到靠近管芯焊盘。 引线包括第一引线和第二引线，其位于引线框架相对于通过管芯焊盘的中心线的相对位置处。 第一和第二引线相对于中心线彼此基本不对称，并具有不同的阻抗值。 多个引线彼此断开。

公开(公告)号：US20140175608A1

公开(公告)日：2014-06-26

申请号：US14190058

申请日：2014-02-25

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811

Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.

Abstract translation: 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同，并且第一区域和第一逻辑电路之间的距离小于第二区域和第二逻辑电路之间的距离。

公开(公告)号：US10784206B2

公开(公告)日：2020-09-22

申请号：US16163614

申请日：2018-10-18

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/498 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L23/50 ,  H01Q21/06 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/66 ,  H01L23/14

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US09908203B2

公开(公告)日：2018-03-06

申请号：US15420140

申请日：2017-01-31

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L25/10 ,  B23K35/02 ,  H01L23/498 ,  B23K35/26 ,  B23K101/40

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

公开(公告)号：US11837552B2

公开(公告)日：2023-12-05

申请号：US17748308

申请日：2022-05-19

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/373 ,  H01L21/52 ,  H01L23/31 ,  H01L23/433 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/00 ,  H01L29/739 ,  H01L29/861 ,  H01L23/051 ,  H01L25/18 ,  H01L23/495 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L25/16 ,  H01L23/50 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22 ,  H01L23/14 ,  H01Q21/06

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/0414 ,  H01L23/145 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01Q21/065 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US10354974B2

公开(公告)日：2019-07-16

申请号：US14736684

申请日：2015-06-11

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Andrew C. Chang ,  Tao Cheng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/528 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

公开(公告)号：US10312222B2

公开(公告)日：2019-06-04

申请号：US15848083

申请日：2017-12-20

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.